Updated and corrected AArch64DeadRegisterDefinitions::ShouldSkip.
Jul 13 2017
I went ahead and committed D35309, so you will likely need to rebase the changes to AArch64InstrAtomics.td and AArch64DeadRegisterDefinitionsPass.cpp. I would also recommend separating out the ThunderX scheduling changes into their own patch, at least when committing.
If at all possible, I would like to see D35309 committed before/with this patch.
Jul 12 2017
May 9 2017
May 3 2017
Apr 28 2017
Right, I clicked the link and it took me to the old code. :)
I'm not sure how f16/f128 would fare there. Probably not well.
Apr 27 2017
Updated to the most recent LLVM git mirror from 2017/04/27.
Several regex and instruction improvements.
Apr 25 2017
Updates to the T99 Scheduler.
Apr 11 2017
I will re-submit with changes shortly - I also have a few more additions to the *.td
file as well.
Apr 6 2017
Mar 5 2017
Updated diff based on Renato's comments.
Mar 2 2017
Mar 1 2017
Diff is based on LLVM trunk from Git mirror on 03/01/2017.
Feb 13 2017
Sorted the ThunderX CPU names alphabetically in AArch64Subtarget.h.
Feb 9 2017
- Added tests for ARMV8.1-A LSE Extensions.
- Added tests in unittests/Support/TargetParserTest.cpp
Hi, can you also please add the relevant tests to unittests/Support/TargetParserTest.cpp? It should be pretty obvious from the context.
Feb 2 2017
This latest changeset is based on ToT from 02/02/2017.
Fixes and corrections as per review comments.
Added test case for ARMV8.1-A and LSE (test/MC/AArch64/armv8.1a-lse.s).
Jan 19 2017
Some comments specifically on the scheduler. Overall the sched-model looks good, although I don't have the detailed latency and micro-architecture information of ThunderX.
A few points you may want to consider :
- You could remove the lines with 'let ResourceCycles = ;' as that's by-default. That would help you reduce size of descriptions in a number of places.
- Same for 'let Latency = 1;'
- I don't know the micro-arch of ThunderX, but is there a typo for the latency of THXT8XWriteVST3 as it exceeds corresponding resource-cycle for the same sched-class. You may want to just double-check that.
- ReadAdvance seems to exceed write latency in some cases, and so you may want to double check that - e.g. ReadI (2) verus WriteI (1).
Best Regards Javed
Jan 18 2017
Support for Cavium ThunderX T8X ARM64 processors.
Sep 3 2015
The diff is based on 3.6.2.