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Oct 12 2017

jbhateja added inline comments to D37660: [ScalarEvolution] Handling Conditional Instruction in SCEV chain..
Oct 12 2017, 8:11 AM

Oct 4 2017

jbhateja added inline comments to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Oct 4 2017, 2:26 AM
jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

can you explain me why? (I may I didn't understood why do we need to process without loop latch)
I thought without latch cannot be evoluted from ICmp evolution.

without latch loop have to me evoluted from previous SCEV operation. isn't it?

I don't understand your statement.

The point is that, in the last loop iteration, latch condition is not true, so replacing it with true is incorrect. If you have:

int values[11];
int i = 0;
do {

values[i] = i != 10;

} while (i++ != 10);

After the loop, values should be { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 }. In the 11th iteration, the comparison will be false. With this patch, we'd store 1 into the values array, even for the last iteration.

Oct 4 2017, 2:21 AM
jbhateja committed rL314886: [X86] Improvement in CodeGen instruction selection for LEAs (re-applying post….
[X86] Improvement in CodeGen instruction selection for LEAs (re-applying post…
Oct 4 2017, 2:04 AM

Oct 3 2017

jbhateja added a comment to D38494: [SCEV] Handling for ICmp occuring in the evolution chain..

For following C and IR references.

Oct 3 2017, 8:32 PM
jbhateja retitled D38494: [SCEV] Handling for ICmp occuring in the evolution chain. from [ScalarEvolution] Handling for ICmp occuring in then evolution chain. to [ScalarEvolution] Handling for ICmp occuring in the evolution chain..
Oct 3 2017, 1:53 AM
jbhateja accepted D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@reviewers, if no more comment I shall be landing this into trunk since required revision changes post acceptance are through.

Oct 3 2017, 1:46 AM · Restricted Project
jbhateja edited reviewers for D38494: [SCEV] Handling for ICmp occuring in the evolution chain., added: sanjoy, hfinkel, junryoungju; removed: llvm-commits.
Oct 3 2017, 12:40 AM
jbhateja created D38494: [SCEV] Handling for ICmp occuring in the evolution chain..
Oct 3 2017, 12:36 AM

Sep 29 2017

jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

@reviewers, please let me know if there are any more comments on this patch.

Sep 29 2017, 11:30 AM
jbhateja added a comment to D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..

I'm not sure about this approach; I don't think most of this needs to be done in the X86 backend at all, and much of it shouldn't even be done in the DAG. Most of the code appears to be better handled in a mixture of SimplifyDemandedVectorElts and SLPVectorizer.

PR33758 was about improving codegen for horizontal reductions, so we'd probably be better off having the backend optimize for @llvm.experimental.vector.reduce.add.* (or the legalized patterns it produces), and then getting the vectorizers to create these properly.

Sep 29 2017, 7:47 AM
jbhateja added reviewers for D36454: [X86] Changes to extract Horizontal addition operation for AVX-512.: zvi, spatel.
Sep 29 2017, 2:08 AM

Sep 28 2017

jbhateja added inline comments to D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..
Sep 28 2017, 8:22 AM
jbhateja updated the diff for D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..
  • Changes to cover more patterns for [f]hadd/[f]sub for AVX512 vector types.
  • Generic routines added which looks at uses / undef operands of an operation for scaling it down.
Sep 28 2017, 8:15 AM
jbhateja committed rL314385: [X86] Adding more cases to horizontal [f]add/[f]sub for avx512..
[X86] Adding more cases to horizontal [f]add/[f]sub for avx512.
Sep 28 2017, 12:42 AM
jbhateja closed D38344: [X86] Adding more cases to horizontal [f]add/[f]sub for avx512. by committing rL314385: [X86] Adding more cases to horizontal [f]add/[f]sub for avx512..
Sep 28 2017, 12:42 AM
jbhateja accepted D38344: [X86] Adding more cases to horizontal [f]add/[f]sub for avx512..
Sep 28 2017, 12:36 AM
jbhateja created D38344: [X86] Adding more cases to horizontal [f]add/[f]sub for avx512..
Sep 28 2017, 12:35 AM

Sep 27 2017

jbhateja accepted D37880: Fix an out-of-bounds shufflevector index bug.

LGTM with a minor comment, please run clang-format. over the changes for better inndentation.

Sep 27 2017, 10:21 PM
jbhateja added a comment to D34596: [X86]: Adding a new priority function 'guided-src' for Scheduler DAG instruction scheduling..

Sorry about this review stalling. To give at least some feedback:

  • We generally want to phase out the SelectionDAG schedulers and only have them do a minimal amount of work. The actual scheduling should happen in the MachineScheduler. So ideally we would not add new features here. (That said I can see why you are doing it here: the MachineScheduler currently does not reorder flags producers/users)
  • I believe none of the currently active LLVM developers is really familiar with the SelectionDAG schedulers.

    I will try to find time for an actual review soon (otherwise please keep pinging).
Sep 27 2017, 10:14 PM
jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

@spatel , @reviewiews , can this land now into trunk ?

I haven't actually looked at the builder changes since you revised them, so I defer to @hfinkel is he's already approved that part.

I don't think that I approved anything yet. I can take a holistic look at the patch later today.

Sep 27 2017, 10:53 AM
jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@jmolloy , @RKSimon , this patch has been reviewd and due to regression was opened again for review, required changes have
been made, can this land now in trunk if there are no more observations from any reviewers.

Sep 27 2017, 4:38 AM · Restricted Project

Sep 26 2017

jbhateja added inline comments to D37880: Fix an out-of-bounds shufflevector index bug.
Sep 26 2017, 3:30 PM
jbhateja updated the diff for D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..
Sep 26 2017, 3:29 PM
jbhateja added a comment to D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..

I don't think we should shrinking operations based on undef inputs. I think we should be shrinking them based on what elements are consumed by their users. There's no reason the shuffles in these reductions have to have undef elements. For integers we may rewrite the shuffle mask to undef in InstCombine if the elements aren't used down stream. But we don't do that for FP.

As an example, why shouldn't we be able use a horizontal add for this

define <4 x double> @fadd_noundef(<8 x double> %x225, <8 x double> %x227) {

  %x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
  %x228 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5 ,i32 13, i32 7, i32 15>
  %x229 = fadd <8 x double> %x226, %x228
  %x230 = shufflevector <8 x double> %x229, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  ret <4 x double> %x230
}
Sep 26 2017, 3:29 PM
jbhateja added reviewers for D37880: Fix an out-of-bounds shufflevector index bug: zvi, aymanmus.
Sep 26 2017, 3:29 PM

Sep 25 2017

jbhateja added a comment to D37880: Fix an out-of-bounds shufflevector index bug.

LGTM

Sep 25 2017, 8:57 AM
jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

@spatel , @reviewiews , can this land now into trunk ?

Sep 25 2017, 5:02 AM

Sep 21 2017

jbhateja updated the diff for D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
  • Updating test case with more than one uses of sqrt / mul.
Sep 21 2017, 10:58 PM
jbhateja committed rL313964: [X86] Updating the test case for FMF propagation..
[X86] Updating the test case for FMF propagation.
Sep 21 2017, 10:50 PM
jbhateja closed D38163: [X86] Updating the test case for FMF propagation. by committing rL313964: [X86] Updating the test case for FMF propagation..
Sep 21 2017, 10:50 PM
jbhateja accepted D38163: [X86] Updating the test case for FMF propagation..
Sep 21 2017, 10:45 PM
jbhateja created D38163: [X86] Updating the test case for FMF propagation..
Sep 21 2017, 10:45 PM
jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@reviewers, required revision change are through, let me know if this can land back.

Sep 21 2017, 12:21 PM · Restricted Project
jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

I've added some more FMF tests at rL313893 which I think this patch will miscompile. Please rebase/update.

As I suggested before, this patch shouldn't try to enable multiple DAG combines with node-level FMF. It's not as straightforward as you might think.

Pick exactly one combine if you want to show that this patch is working as intended. The llvm.muladd intrinsic test that you have here with a target that supports 'fma' (not plain x86) seems like a good choice to me. If we have a strict op in IR, it should produce an fma instruction. If we have a fast op in IR, it should produce the simpler fmul instruction?

My understanding and code changes are based LLVM Ref Manual 's section about Fast-Math flags" (http://llvm.org/docs/LangRef.html#fast-math-flags)

Which say for FMF flag NaN "Allow optimizations to assume the arguments and result are not NaN".

Now in following case which has been added by you

%y = call float @llvm.sqrt.f32(float %x)
%z = fdiv fast float 1.0, %y
ret float %z

We dont have fast flag over intrinsic but DAGCombining for fdiv sees a fast flag and assume result (%z) and arguments (constant , %y) as not a Nan and goes ahead and generates a reciprocal sqrt. If you remove fast from fdiv and add it to intrinsic then FMF opt at fdiv will not kick in.

Can you please let me know what you expected here.

I expect that the sqrt result is strict. Ie, it should use sqrtss if this is x86-64. We're not allowed to use rsqrtss and lose precision on that op.

That said, my memory of exactly how op-level FMF should work is fuzzy. If anyone else remembers or can link to threads where we've discussed this, please feel free to jump in. :)

Sep 21 2017, 12:16 PM
jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

I've added some more FMF tests at rL313893 which I think this patch will miscompile. Please rebase/update.

As I suggested before, this patch shouldn't try to enable multiple DAG combines with node-level FMF. It's not as straightforward as you might think.

Pick exactly one combine if you want to show that this patch is working as intended. The llvm.muladd intrinsic test that you have here with a target that supports 'fma' (not plain x86) seems like a good choice to me. If we have a strict op in IR, it should produce an fma instruction. If we have a fast op in IR, it should produce the simpler fmul instruction?

Sep 21 2017, 11:53 AM
jbhateja added inline comments to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
Sep 21 2017, 3:10 AM
jbhateja updated the diff for D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
  • Review comments resolutions.
Sep 21 2017, 3:07 AM
jbhateja committed rL313869: [X86] Adding a testpoint for fast-math flags propagation..
[X86] Adding a testpoint for fast-math flags propagation.
Sep 21 2017, 2:55 AM
jbhateja closed D38127: [X86] Adding a testpoint for fast-math flags propagation. by committing rL313869: [X86] Adding a testpoint for fast-math flags propagation..
Sep 21 2017, 2:55 AM
jbhateja accepted D38127: [X86] Adding a testpoint for fast-math flags propagation..
Sep 21 2017, 2:50 AM
jbhateja created D38127: [X86] Adding a testpoint for fast-math flags propagation..
Sep 21 2017, 2:49 AM
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
Sep 21 2017, 12:15 AM · Restricted Project

Sep 19 2017

jbhateja added inline comments to D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..
Sep 19 2017, 4:15 AM
jbhateja updated the diff for D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..
Sep 19 2017, 12:10 AM

Sep 18 2017

jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

Ping @reviewers.

Sep 18 2017, 6:32 PM

Sep 17 2017

jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

ping @ reviewers.

Sep 17 2017, 12:04 PM
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Updating tests for reported PRs for initial patch.
Sep 17 2017, 11:36 AM · Restricted Project
jbhateja committed rL313490: Adding test cases for PR34629 & PR34634..
Adding test cases for PR34629 & PR34634.
Sep 17 2017, 11:17 AM
jbhateja closed D37962: Adding test cases for PR34629 & PR34634. by committing rL313490: Adding test cases for PR34629 & PR34634..
Sep 17 2017, 11:17 AM
jbhateja accepted D37962: Adding test cases for PR34629 & PR34634..
Sep 17 2017, 11:07 AM
jbhateja created D37962: Adding test cases for PR34629 & PR34634..
Sep 17 2017, 11:06 AM
jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@RKSimon, @Reviewers, revision was in accepted state earlier and fix to counter reported issues post commit to trunk has been fixed. Please do let me know if another acceptance is needed to land this again.

Sep 17 2017, 12:38 AM · Restricted Project
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Undefining result operand of factored statement to preserve SSA nature of Machine IR.
  • This fixes reperted PR 34634 and PR 34629 and build-bot failures reported.
Sep 17 2017, 12:24 AM · Restricted Project

Sep 16 2017

jbhateja updated the diff for D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
  • Rebase from trunk.
  • More changes to cover review comments.
  • Test usage of fast-math flags over nodes at some places, it fixes PR34558.
  • More places where flags over node needs to be checked, to be done incrementally.
Sep 16 2017, 6:24 AM

Sep 15 2017

jbhateja added inline comments to D37880: Fix an out-of-bounds shufflevector index bug.
Sep 15 2017, 10:35 PM
jbhateja added a comment to D37880: Fix an out-of-bounds shufflevector index bug.
Sep 15 2017, 3:06 AM

Sep 14 2017

jbhateja committed rL313343: [X86] PR32755 : Improvement in CodeGen instruction selection for LEAs..
[X86] PR32755 : Improvement in CodeGen instruction selection for LEAs.
Sep 14 2017, 10:32 PM
jbhateja closed D35014: [X86] Improvement in CodeGen instruction selection for LEAs. by committing rL313343: [X86] PR32755 : Improvement in CodeGen instruction selection for LEAs..
Sep 14 2017, 10:32 PM · Restricted Project
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Few synthetic changes.
Sep 14 2017, 10:18 PM · Restricted Project

Sep 13 2017

jbhateja updated the diff for D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
  • Review comments resolution.
Sep 13 2017, 9:16 AM
jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

@lsaba, @reviewers , waiting for your LGTM or any remaining comments on this.
Thanks

Sep 13 2017, 6:28 AM · Restricted Project
jbhateja updated the diff for D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
  • Review comments handling.
Sep 13 2017, 6:18 AM

Sep 12 2017

jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

@reviewers, are there any more comments apart from last comments, this is just to save iteration, thanks for your time in reviews.

Sep 12 2017, 8:00 PM
jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

Ping @reviewers

Sep 12 2017, 5:41 PM
jbhateja updated the diff for D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
  • Review comments resolution + flags propagation over operands.
Sep 12 2017, 8:16 AM

Sep 11 2017

jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

ping @ reviewers.

Sep 11 2017, 9:48 AM · Restricted Project
jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

There is a functional difference from this improvement (several FP intrinsics should now correctly propagate flags), but I'm not sure if it's visible without fixing something else in DAGCombiner to recognize the flags.

How does this work if an instruction maps to multiple nodes? For example, the FMA intrinsic can map to 2 nodes?

Sep 11 2017, 9:17 AM
jbhateja added a comment to D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..

@RKSimon Anything else or should I check this in as NFC.

Sep 11 2017, 7:53 AM
jbhateja added reviewers for D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management.: spatel, RKSimon.
Sep 11 2017, 6:48 AM
jbhateja created D37686: [DAG] Consolidating Instruction->SDNode Flags propagation in one class for better code management..
Sep 11 2017, 6:46 AM
jbhateja updated the diff for D34596: [X86]: Adding a new priority function 'guided-src' for Scheduler DAG instruction scheduling..
Sep 11 2017, 6:14 AM

Sep 10 2017

jbhateja added a comment to D37616: [X86] PR34149 Suboptimal codegen for fast minnum and maxnum..

I might be missing some context here. If we have fast/nnan on these calls, then can't we simplify this in IR to fmp+select and not have to deal with this in the backend? The intrinsics only exist to make sure that NaN behavior in IR meets the higher level standards, so if we have nnan, then we don't need the intrinsic?

Intrinsic function defer code geneation/expansion to backend this give backend control over geneating efficient code as per specific target.

It's incorrect that intrinsics are passed unaltered to the backend for expansion/optimization. See the optimizations for both generic and target-specific intrinsics in InstCombiner::visitCallInst().

Again, I may be missing some context - who created this IR? Creating a 'call fast llvm.maxnum()' just doesn't make sense to me, so if we can fix that in IR, we should do that. The intrinsic inhibits the large number of potential optimizations for fcmp+select that we have in IR. No target should benefit from having extra NaN semantics requirements provided by the intrinsic that are then overridden by FMF.

Please split the FlagsAcquirer diff into a separate patch.

Sep 10 2017, 10:32 AM

Sep 9 2017

jbhateja added a comment to D37616: [X86] PR34149 Suboptimal codegen for fast minnum and maxnum..

I might be missing some context here. If we have fast/nnan on these calls, then can't we simplify this in IR to fmp+select and not have to deal with this in the backend? The intrinsics only exist to make sure that NaN behavior in IR meets the higher level standards, so if we have nnan, then we don't need the intrinsic?

Sep 9 2017, 10:12 AM
jbhateja updated the diff for D37616: [X86] PR34149 Suboptimal codegen for fast minnum and maxnum..
  • Consolidating Instruction->SDNode Flags propagation in one class.
Sep 9 2017, 9:54 AM

Sep 8 2017

jbhateja closed D37613: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum'.

Closing with commit rL312778: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum

Sep 8 2017, 2:47 AM
jbhateja accepted D37613: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum'.
Sep 8 2017, 2:47 AM
jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Rebasing again.
  • Adding a check for subtarget feature Slow3OpLEA in pattern matching.
Sep 8 2017, 2:44 AM · Restricted Project
jbhateja edited reviewers for D37616: [X86] PR34149 Suboptimal codegen for fast minnum and maxnum., added: sanjoy, RKSimon, spatel, craig.topper; removed: llvm-commits.
Sep 8 2017, 2:40 AM
jbhateja created D37616: [X86] PR34149 Suboptimal codegen for fast minnum and maxnum..
Sep 8 2017, 2:38 AM
jbhateja committed rL312778: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and….
[X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and…
Sep 8 2017, 2:17 AM
jbhateja closed D37614: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum' by committing rL312778: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and….
Sep 8 2017, 2:17 AM
jbhateja accepted D37614: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum'.
Sep 8 2017, 2:13 AM
jbhateja created D37614: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum'.
Sep 8 2017, 2:12 AM
jbhateja created D37613: [X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum'.
Sep 8 2017, 2:12 AM

Sep 6 2017

jbhateja added a comment to D35014: [X86] Improvement in CodeGen instruction selection for LEAs..

3-Ops LEA are costly starting target SandyBridge , is there a limitation in the code for the targets this transformation works on? If not I think there should be.
you can check the Slow3OpsLEA feature for the full list of targets.

Sep 6 2017, 4:48 AM · Restricted Project
jbhateja added a comment to D36454: [X86] Changes to extract Horizontal addition operation for AVX-512..

I think we should try to combine based on the add only being used by the extract_vector_elt. Turn the add into a 128-bit add being fed by extract_subvectors. Similarly if we see an add only being used by an extract_subvector we can shrink that add too and push the extracts up. This type of transform feels more generally useful because it will allow us to narrow many more adds in this code. This will enable EVEX->VEX to use a smaller encoding. We can apply this to many other opcodes as well.

If we do this early enough we should be able to shrink the add before the horizontal add detection.

Sep 6 2017, 12:43 AM

Sep 5 2017

jbhateja committed rL312614: Updating a test reference for rL312608..
Updating a test reference for rL312608.
Sep 5 2017, 8:59 PM
jbhateja closed D37501: Updating a test reference for rL312608. by committing rL312614: Updating a test reference for rL312608..
Sep 5 2017, 8:59 PM
jbhateja accepted D37501: Updating a test reference for rL312608..
Sep 5 2017, 8:56 PM
jbhateja created D37501: Updating a test reference for rL312608..
Sep 5 2017, 8:52 PM
jbhateja committed rL312608: [X86] Allow cross-lane permutations for sub targets supporting AVX2..
[X86] Allow cross-lane permutations for sub targets supporting AVX2.
Sep 5 2017, 8:01 PM
jbhateja closed D37388: [X86] Allow cross-lane permutations for sub targets supporting AVX2. by committing rL312608: [X86] Allow cross-lane permutations for sub targets supporting AVX2..
Sep 5 2017, 8:01 PM
jbhateja updated the diff for D37388: [X86] Allow cross-lane permutations for sub targets supporting AVX2..
  • Formatting changes
Sep 5 2017, 7:53 PM

Sep 4 2017

jbhateja updated the diff for D35014: [X86] Improvement in CodeGen instruction selection for LEAs..
  • Fine tuning pattern matching condition.
  • Formatting changes.
Sep 4 2017, 9:55 PM · Restricted Project
jbhateja updated the diff for D37388: [X86] Allow cross-lane permutations for sub targets supporting AVX2..
  • Reverting lit script change.
Sep 4 2017, 11:34 AM
jbhateja updated the diff for D37388: [X86] Allow cross-lane permutations for sub targets supporting AVX2..
Sep 4 2017, 11:27 AM

Sep 3 2017

jbhateja committed rL312444: Test commit access in clang..
Test commit access in clang.
Sep 3 2017, 8:30 AM
jbhateja closed D37426: Test commit access in clang. by committing rL312444: Test commit access in clang..
Sep 3 2017, 8:30 AM
jbhateja accepted D37426: Test commit access in clang..
Sep 3 2017, 8:25 AM