address @jrtc27's comment, thanks! I forget RISCVISAInfo include XLen..
Fri, Jul 23
address arichardson's comment, thanks!
Thu, Jul 22
store target-features string as module flag.
Tue, Jul 20
Why can't we just save target-features itself as a module flag instead of inventing yet another equivalent encoding? Especially since a long bitfield is brittle, you can't reorder or remove elements without breaking bitcode compatibility.
Sun, Jul 18
rebase on D105168.
This all looks good to me except some tidy warning.
wait for others comments.
I think the difference between of order and unordered load is when the exception happens on memory access,
and the document said "However, using this intrinsic prevents exceptions on memory access to masked-off lanes."
IMO, it makes sense to me to assume mgather is unordered access, because intrinsic users have to set masked-off to avoid exception.
Thu, Jul 15
Tue, Jul 13
Mon, Jul 12
Thu, Jul 8
rebase on D102582
report a error if target-abi module flag is is empty.
address jrtc27's comment.
Wed, Jul 7
Mon, Jul 5
Sun, Jul 4
Update test cases.
Thu, Jul 1
Tue, Jun 29
Mon, Jun 28
This all looks good to me except adding back the asm check.
BTW, do we need to attach the half-precision floating point spec link?
May 31 2021
Revert to previous revision Diff 347356 and add empty module flag could be empty in test.
May 29 2021
Good catch! LGTM.
May 27 2021
address @luismarques's comments.
May 24 2021
- Handle an empty module flag.
So sorry I forgot to run the clang regresion tests before.
- Add empty module flag test and combine all tests into one. It is simiar to compress.ll
I think this patch is similar to D73339 but it fixes obj file attribute, it is not going to fix different target feature in one complication unit problem.
May 23 2021
clang or clang+llc your test with my patch the arch attribute is still rv64i2p0, does it break your use cases?
update test to show asm has F instructions.
May 22 2021
I got the similar IR during LTO because the clang driver would not pass the -mattr option to lto code generator.
May 21 2021
May 17 2021
address Craig's comments, thanks!
addres https://reviews.llvm.org/D71387#2762120, compute a default ABI for comparison rather than report an error when missing -mabi
May 16 2021
Okay. Please let me know if you want me to review anything.
We had encoded the target-abi into module now, but I feel it does not make sense to
support overwrite ABI option and datalayout in TargetMahcine/IR by target-abi module flag in IR.
So I think maybe passing the target-abi option by clang driver can make anything more simple, the only one limitation is users need to specific -mabi in below cases at the last command.clang -target riscv64-unknown-elf a.c -flto -march=rv64gc -mabi=lp64f -o a.o clang -target riscv64-unknown-elf b.c -flto -march=rv64gc -mabi=lp64f -o b.o clang -target riscv64-unknown-elf a.o b.o -flto -march=rv64gc -o foo
We should treat a missing -mabi= as an implicit -mabi=whatever-the-default-is for consistency with non-LTO. So yes, if the default ABI differs from what you've compiled the .o's with, you should have to provide it. This is needed already _anyway_ for multilib toolchains to determine the right library search path, though there are cases currently when you can get away without providing it, at least with Clang.
- address @jrtc27' comment
- change report_fatal_error as errs() because report_fatal_error will ask users to submit a bug report, it does not make sense.
- combine two error message as one.
Pass -target-abi option into LTO codegenerator base on D102582 patch.
May 9 2021
Good catch, LGTM!
May 7 2021
Good catch! LGTM!
May 5 2021
May 3 2021
Hi, I would like to add ilp32e ABI support in llvm
Is there anyone working on this?
It seem the one thing missed is ilp32e ABI should disallow D ISA extension.
Is there anything else?
May 2 2021
LGTM. Thanks for improvement!
Apr 28 2021
Apr 27 2021
Thanks for clarification, LGTM.
Apr 26 2021
Select the immediate during isel does make sense to me, but unfortunately there are some cases have a slower result.
Do you know is there any cases which have better instruction order and reduce register spilling when apply the new scheme?
I'm just afraid of the new one would be always generate the slower instruction order.
Apr 25 2021
Apr 21 2021
Apr 20 2021
Apr 19 2021
Apr 18 2021
LGTM. Please remove the ASM check in upstream patches.
Look good to me.
BTW, we also need to update the document later.
Apr 17 2021
I think you also need to handle PermuteOperands field?
PermuteOperands performs the order permutation for non-masked and masked intrinsics when the operand order is different to builtins.
Apr 16 2021
Address the Craig's comments.
Great, let's wait and see for a few days to see if it lands, and if so how much that recovers then.
Do you mean revert https://github.com/llvm/llvm-project/compare/a3bfddbb6a27...59d5b8c27b43?
Was there any more progress on this? If not, let's revert for now to not permanently slow down tests by over 20%.
Apr 15 2021
I think using this proxy header for testing seems good.
The fact that we're running the optimization pipeline in these tests might be to blame. Might also be that riscv_vector.h is currently about 71000 lines which probably isn't quick to parse.
Apr 14 2021
Apr 13 2021
Apr 12 2021
address Jim's comment.