Page MenuHomePhabricator
Feed Advanced Search

Today

aemerson committed rG3c7e8d6d0eb0: Fix sdk version test to use 99.99.99 as a max dummy version instead of 10.99.99. (authored by aemerson).
Fix sdk version test to use 99.99.99 as a max dummy version instead of 10.99.99.
Mon, Jul 6, 4:53 PM

Sat, Jul 4

aemerson committed rG85e144329cff: [profile] Mark gcov test as unsupported on Darwin. (authored by aemerson).
[profile] Mark gcov test as unsupported on Darwin.
Sat, Jul 4, 10:46 AM

Wed, Jul 1

aemerson updated the diff for D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy.

Address comments. Use copy instead of buildAnyExtOrTrunc.

Wed, Jul 1, 3:09 PM · Restricted Project

Fri, Jun 26

aemerson added a comment to D82615: [HWASan] [GlobalISel] Add +tagged-globals backend feature for GlobalISel.

I'm not familiar with these types globals. Do you think there's any issue with the current design that would make it difficult to generate optimal code in future?

Fri, Jun 26, 3:10 PM · Restricted Project, Restricted Project

Thu, Jun 25

aemerson committed rG97a34b5f8d2e: [AArch64][GlobalISel] Fix extended shift addressing mode selection not handling… (authored by aemerson).
[AArch64][GlobalISel] Fix extended shift addressing mode selection not handling…
Thu, Jun 25, 5:30 PM
aemerson added a comment to D81992: [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support..
%6:_(s32) = nsw G_SUB %3:_, %5:_
%7:_(s16) = G_TRUNC %6:_(s32)
%8:_(s64) = G_SEXT %7:_(s16)

which then gets converted to

%6:_(s32) = nsw G_SUB %3:_, %5:_
%16:_(s64) = G_ANYEXT %6:_(s32)
%8:_(s64) = G_SEXT_INREG %16:_, 16

The truncation has been lost, and we eventually end up with

The anyext is fine there, the SEXT_INREG should do the right thing and sign extend from bit 16, however it looks like we have a bug in the selector in this case. Fix incoming.

Thu, Jun 25, 5:29 PM · Restricted Project
aemerson added a comment to D81992: [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support..
%6:_(s32) = nsw G_SUB %3:_, %5:_
%7:_(s16) = G_TRUNC %6:_(s32)
%8:_(s64) = G_SEXT %7:_(s16)

which then gets converted to

%6:_(s32) = nsw G_SUB %3:_, %5:_
%16:_(s64) = G_ANYEXT %6:_(s32)
%8:_(s64) = G_SEXT_INREG %16:_, 16

The truncation has been lost, and we eventually end up with

Thu, Jun 25, 5:29 PM · Restricted Project

Wed, Jun 24

aemerson committed rG090c108d04e2: Don't inline dynamic allocas that simplify to huge static allocas. (authored by aemerson).
Don't inline dynamic allocas that simplify to huge static allocas.
Wed, Jun 24, 5:57 PM
aemerson closed D81765: Don't inline dynamic allocas that simplify to huge static allocas..
Wed, Jun 24, 5:57 PM · Restricted Project
aemerson updated the diff for D81765: Don't inline dynamic allocas that simplify to huge static allocas..

Add some CHECK lines, add FIXME comment, update description/commit message.

Wed, Jun 24, 5:56 PM · Restricted Project
aemerson added a comment to D81765: Don't inline dynamic allocas that simplify to huge static allocas..

Not sure I follow this in the patch description:
"Avoid inlining functions if this would result, as even if we didn't hoist the alloca it would remain an dynamic alloca in the caller body."

What would be different between: inlining and not hoisting the alloca, or not inlining?

That's a poor description on my part, you can disregard it. If we inlined it but didn't hoist the alloca from the never-executed block, it would still cause the function to have a dynamic alloca present and perhaps negatively impact codegen as Eli alluded to earlier in this thread.

Wed, Jun 24, 1:34 PM · Restricted Project
aemerson added inline comments to D81765: Don't inline dynamic allocas that simplify to huge static allocas..
Wed, Jun 24, 11:55 AM · Restricted Project
aemerson updated the diff for D81765: Don't inline dynamic allocas that simplify to huge static allocas..

Add tests and fix not scaling the alloc size by the type size.

Wed, Jun 24, 11:55 AM · Restricted Project

Tue, Jun 23

aemerson added inline comments to D81765: Don't inline dynamic allocas that simplify to huge static allocas..
Tue, Jun 23, 7:59 PM · Restricted Project
aemerson committed rGfceadbcb335d: [AArch64][GlobalISel] Improve codegen for some constant vectors by using… (authored by aemerson).
[AArch64][GlobalISel] Improve codegen for some constant vectors by using…
Tue, Jun 23, 7:27 PM
aemerson closed D82340: [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.
Tue, Jun 23, 7:27 PM · Restricted Project
aemerson added a comment to D81765: Don't inline dynamic allocas that simplify to huge static allocas..
In D81765#2109656, @jfb wrote:
In D81765#2090952, @jfb wrote:

One thing I'd like to make sure we don't break:

__attribute__((always_inline))
char *stack_allocate(size_t size) {
  if (size < threshold)
    return alloca(size);
  return malloc(size);
}

This should always inline. Is it still the case? It turns out that we have Important Code which relies on this...

Can you check this?

Tue, Jun 23, 6:21 PM · Restricted Project
aemerson added inline comments to D81765: Don't inline dynamic allocas that simplify to huge static allocas..
Tue, Jun 23, 11:48 AM · Restricted Project
aemerson added a comment to D82329: [SVE] Fix invalid Scalable to fixed width vetor type demotion in LLT.

Perhaps this change is good enough? We call computeValueLLTs just before lowerFormalArguments, which will detect the scalable type and fall back anyway even if the LLT type is wrong. The other option is to add yet another fallBackOnDAGISel type callback that allows the backend to reject certain types before we create the vregs.

Tue, Jun 23, 11:15 AM · Restricted Project
aemerson added inline comments to D82340: [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.
Tue, Jun 23, 10:10 AM · Restricted Project

Mon, Jun 22

aemerson added a comment to D81765: Don't inline dynamic allocas that simplify to huge static allocas..

Ping.

Mon, Jun 22, 11:25 PM · Restricted Project
aemerson added a comment to D82329: [SVE] Fix invalid Scalable to fixed width vetor type demotion in LLT.

I talked to Christopher offline, and he said this code is in fact getting hit with SVE enabled. Is D81557 working correctly?

Mon, Jun 22, 10:32 PM · Restricted Project
aemerson added inline comments to D82340: [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.
Mon, Jun 22, 6:49 PM · Restricted Project
aemerson created D82340: [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.
Mon, Jun 22, 6:49 PM · Restricted Project
aemerson accepted D81979: [AArch64][GlobalISel] Port buildvector -> dup pattern from AArch64ISelLowering.

LGTM.

Mon, Jun 22, 6:49 PM · Restricted Project

Sat, Jun 20

aemerson updated the diff for D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy.

Use computeNumSignBits() since we can tolerate extra copies with SEXT_INREG.

Sat, Jun 20, 10:34 AM · Restricted Project

Fri, Jun 19

aemerson committed rG1feeecf224c6: [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support. (authored by aemerson).
[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.
Fri, Jun 19, 1:37 PM
aemerson closed D81992: [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support..
Fri, Jun 19, 1:37 PM · Restricted Project
aemerson added inline comments to D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy.
Fri, Jun 19, 1:04 PM · Restricted Project

Thu, Jun 18

aemerson committed rG84167a8d58e8: [docs] Clarify semantics of ordered fadd/fmul reductions. (authored by aemerson).
[docs] Clarify semantics of ordered fadd/fmul reductions.
Thu, Jun 18, 9:14 AM
aemerson closed D82034: [docs] Clarify semantics of ordered fadd/fmul reductions..
Thu, Jun 18, 9:13 AM · Restricted Project

Wed, Jun 17

aemerson added a parent revision for D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy: D81992: [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support..
Wed, Jun 17, 4:44 PM · Restricted Project
aemerson added a child revision for D81992: [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.: D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy.
Wed, Jun 17, 4:44 PM · Restricted Project
aemerson updated the diff for D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy.

Move the combine to post legalizer, now matching what ends up coming out of the legalizer for AArch64 which is a G_SEXT_INREG.

Wed, Jun 17, 4:44 PM · Restricted Project
aemerson updated the diff for D82034: [docs] Clarify semantics of ordered fadd/fmul reductions..
Wed, Jun 17, 3:40 PM · Restricted Project
aemerson added inline comments to D82034: [docs] Clarify semantics of ordered fadd/fmul reductions..
Wed, Jun 17, 3:39 PM · Restricted Project
aemerson created D82034: [docs] Clarify semantics of ordered fadd/fmul reductions..
Wed, Jun 17, 11:18 AM · Restricted Project
aemerson added a comment to D81979: [AArch64][GlobalISel] Port buildvector -> dup pattern from AArch64ISelLowering.

So is this still applicable to GISel? If not can we remove that restriction.

Wed, Jun 17, 11:18 AM · Restricted Project
aemerson accepted D81956: GlobalISel: Fix some artifact combiner worklist inconsistencies.
Wed, Jun 17, 10:13 AM · Restricted Project
aemerson added a comment to D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy.

This doesn't seem necessary for correctness? I think we do need some optimizing combines in the legalizer itself, but I assumed we would start putting those in a distinct place

Wed, Jun 17, 10:13 AM · Restricted Project
aemerson created D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy.
Wed, Jun 17, 12:30 AM · Restricted Project

Tue, Jun 16

aemerson created D81992: [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support..
Tue, Jun 16, 11:57 PM · Restricted Project
aemerson added inline comments to D81956: GlobalISel: Fix some artifact combiner worklist inconsistencies.
Tue, Jun 16, 10:55 PM · Restricted Project
aemerson added inline comments to D81899: [gicombiner] Unify common state for current targets into CommonTargetCombinerHelperState.
Tue, Jun 16, 10:23 PM · Restricted Project
aemerson added a comment to D81979: [AArch64][GlobalISel] Port buildvector -> dup pattern from AArch64ISelLowering.

What's the reason for avoiding matching a constant lane build_vector?

Tue, Jun 16, 10:23 PM · Restricted Project
aemerson added a comment to D81557: [SVE] Fall back on DAG ISel at -O0 when encountering scalable types.

Yes, but I meant add them to the existing test file in test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

Tue, Jun 16, 11:32 AM · Restricted Project

Mon, Jun 15

aemerson accepted D81897: [AArch64][GlobalISel] Avoid creating redundant ubfx when selecting G_ZEXT.

LGTM.

Mon, Jun 15, 9:28 PM · Restricted Project
aemerson committed rG1035a416a694: [AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates. (authored by aemerson).
[AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates.
Mon, Jun 15, 8:56 PM
aemerson closed D81893: [AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates..
Mon, Jun 15, 8:55 PM · Restricted Project
aemerson added inline comments to D81893: [AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates..
Mon, Jun 15, 5:42 PM · Restricted Project
aemerson created D81893: [AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates..
Mon, Jun 15, 4:35 PM · Restricted Project
aemerson accepted D81876: [GlobalISel] Combine (0 * x) -> 0.

LGTM but I think this is unnecessary since it was a simple fix to just avoid generating useless multiplies in fc905ae003df

Mon, Jun 15, 3:29 PM · Restricted Project
aemerson accepted D81875: [GlobalISel] Look through extends etc in CombinerHelper::matchConstantOp.
Mon, Jun 15, 3:29 PM · Restricted Project
aemerson committed rGfc905ae003df: [GlobalISel] Don't emit multiply by magic constant for zero memset values. (authored by aemerson).
[GlobalISel] Don't emit multiply by magic constant for zero memset values.
Mon, Jun 15, 2:57 PM
aemerson added a comment to D80249: CodeGen: Don't lazily construct MachineFunctionInfo.

Is there no reasonable default MFI we can create?

Mon, Jun 15, 12:04 PM · Restricted Project
aemerson accepted D81436: [AArch64][GlobalISel] Add G_EXT and select ext using it.

LGTM.

Mon, Jun 15, 12:04 PM · Restricted Project

Fri, Jun 12

aemerson updated the diff for D81765: Don't inline dynamic allocas that simplify to huge static allocas..

Instead of avoiding hoisting, avoid inlining altogether.

Fri, Jun 12, 6:15 PM · Restricted Project
aemerson added a comment to D81765: Don't inline dynamic allocas that simplify to huge static allocas..

Independent of the thresholds, I'd be very cautious about turning a static alloca into a dynamic alloca. Our code generation isn't very sophisticated in a lot of cases; it often requires a "base pointer" to be generated in a fixed register. This leads to a issues even if the alloca never runs: there's a performance penalty due to allocating the base pointer, and we can potentially break inline asm. We don't want to be doing that; if it comes down to either emitting a dynamic alloca or refusing to inline, refusing to inline is probably better.

Fri, Jun 12, 5:08 PM · Restricted Project
aemerson added a reviewer for D81765: Don't inline dynamic allocas that simplify to huge static allocas.: jfb.
Fri, Jun 12, 2:49 PM · Restricted Project
aemerson created D81765: Don't inline dynamic allocas that simplify to huge static allocas..
Fri, Jun 12, 2:49 PM · Restricted Project
aemerson committed rG1cbebd95de2b: [AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection. (authored by aemerson).
[AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection.
Fri, Jun 12, 12:07 PM
aemerson closed D81419: [AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection..
Fri, Jun 12, 12:06 PM · Restricted Project
aemerson added inline comments to D81436: [AArch64][GlobalISel] Add G_EXT and select ext using it.
Fri, Jun 12, 11:26 AM · Restricted Project
aemerson accepted D81557: [SVE] Fall back on DAG ISel at -O0 when encountering scalable types.

LGTM but please also add a test that we fall back to DAG for the argument lowering in the arm64-fallbacks.ll test.

Fri, Jun 12, 10:19 AM · Restricted Project

Thu, Jun 11

aemerson added inline comments to D81436: [AArch64][GlobalISel] Add G_EXT and select ext using it.
Thu, Jun 11, 6:43 PM · Restricted Project
aemerson accepted D81322: [AArch64][GlobalISel] Allow G_DUP for elements smaller than 32 B..

LGTM.

Thu, Jun 11, 6:43 PM · Restricted Project
aemerson added a comment to D81557: [SVE] Fall back on DAG ISel at -O0 when encountering scalable types.

Do we also need to check here for SVE arguments? I doubt the current call lowering is going to work with scalable vectors so we might need a check there too in lowerFormalArguments.

Thu, Jun 11, 5:38 PM · Restricted Project

Tue, Jun 9

aemerson committed rG075890ca551a: [AArch64] Move RegisterBankInfo.cpp/h to GISel. (authored by aemerson).
[AArch64] Move RegisterBankInfo.cpp/h to GISel.
Tue, Jun 9, 11:58 PM
aemerson accepted D81502: GlobalISel: Make default implementation of legalizeCustom unreachable.
Tue, Jun 9, 11:25 PM · Restricted Project
aemerson committed rG938cc573ee1a: [AArch64][GlobalISel] Select G_ADD_LOW into a MOVaddr pseudo. (authored by aemerson).
[AArch64][GlobalISel] Select G_ADD_LOW into a MOVaddr pseudo.
Tue, Jun 9, 5:10 PM
aemerson closed D81512: [AArch64][GlobalISel] Select G_ADD_LOW into a MOVaddr pseudo..
Tue, Jun 9, 5:10 PM · Restricted Project
aemerson created D81512: [AArch64][GlobalISel] Select G_ADD_LOW into a MOVaddr pseudo..
Tue, Jun 9, 3:28 PM · Restricted Project
aemerson accepted D81492: [AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes.

LGTM.

Tue, Jun 9, 2:54 PM · Restricted Project

Mon, Jun 8

aemerson accepted D81182: [AArch64][GlobalISel] Select trn1 and trn2.

LGTM.

Mon, Jun 8, 4:39 PM · Restricted Project
aemerson added inline comments to D81322: [AArch64][GlobalISel] Allow G_DUP for elements smaller than 32 B..
Mon, Jun 8, 4:09 PM · Restricted Project
aemerson updated the diff for D81419: [AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection..

Update test.

Mon, Jun 8, 4:06 PM · Restricted Project
aemerson created D81419: [AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection..
Mon, Jun 8, 12:41 PM · Restricted Project
aemerson added a comment to D81368: [SVE] Disable Global and Fast ISel at -O0 if the SVE feature is found.

Hi @aemerson, do you know if there are any plans to add scalable vector support to global isel for AArch64?

Mon, Jun 8, 9:56 AM · Restricted Project

Jun 5 2020

aemerson accepted D81221: [AArch64][GlobalISel] Move dup optimization into post-legalizer combiner.

LGTM.

Jun 5 2020, 4:16 PM · Restricted Project

Jun 4 2020

aemerson committed rGe53f55805784: [AArch64][GlobalISel] Move GlobalISel source files to a dedicated subdir. (authored by aemerson).
[AArch64][GlobalISel] Move GlobalISel source files to a dedicated subdir.
Jun 4 2020, 11:04 AM
aemerson closed D81116: [AArch64][GlobalISel] Move GlobalISel source files to a dedicated subdir.
Jun 4 2020, 11:03 AM · Restricted Project

Jun 3 2020

aemerson accepted D80923: GlobalISel: Start defining strict FP instructions.

Ok then.

Jun 3 2020, 3:29 PM · Restricted Project
aemerson accepted D81112: [AArch64][GlobalISel] Add selection support for rev16, rev32, and rev64.

LGTM with nit/

Jun 3 2020, 2:55 PM · Restricted Project
aemerson accepted D81049: [AArch64][GlobalISel] Select uzp1 and uzp2.

LGTM.

Jun 3 2020, 1:46 PM · Restricted Project
aemerson created D81116: [AArch64][GlobalISel] Move GlobalISel source files to a dedicated subdir.
Jun 3 2020, 1:46 PM · Restricted Project

Jun 2 2020

aemerson added inline comments to D80923: GlobalISel: Start defining strict FP instructions.
Jun 2 2020, 6:07 PM · Restricted Project
aemerson accepted D80898: AArch64/GlobalISel: Fix assert on call returning 0 sized type.

I guess we have the types for doing pointer arithmetic. LGTM.

Jun 2 2020, 5:35 PM · Restricted Project
aemerson accepted D80969: [AArch64][GlobalISel] Select zip1 and zip2.

Very nice!

Jun 2 2020, 5:02 PM · Restricted Project

Jun 1 2020

aemerson committed rG19ff00dab875: [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg… (authored by aemerson).
[AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg…
Jun 1 2020, 4:17 PM
aemerson committed rGf573d489b6fc: [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize. (authored by aemerson).
[AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize.
Jun 1 2020, 4:17 PM
aemerson closed D78465: [AArch64][GlobalISel] Split G_GLOBAL_VALUE into ADRP + G_ADD_LOW and optimize..
Jun 1 2020, 4:17 PM · Restricted Project
aemerson closed D80834: [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg between the two instructions..
Jun 1 2020, 4:17 PM · Restricted Project
aemerson added inline comments to D80834: [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg between the two instructions..
Jun 1 2020, 3:11 PM · Restricted Project
aemerson updated the diff for D80834: [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg between the two instructions..

Add a test case for a use before the ADRP.

Jun 1 2020, 3:11 PM · Restricted Project

May 29 2020

aemerson created D80834: [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg between the two instructions..
May 29 2020, 1:06 PM · Restricted Project

May 28 2020

aemerson committed rGa0c90b5b2ad6: [AArch64][GlobalISel] Enable extending loads combines post-legalization. (authored by aemerson).
[AArch64][GlobalISel] Enable extending loads combines post-legalization.
May 28 2020, 11:26 PM
aemerson closed D80458: [AArch64][GlobalISel] Enable extending loads combines post-legalization..
May 28 2020, 11:25 PM · Restricted Project
aemerson added a comment to D80458: [AArch64][GlobalISel] Enable extending loads combines post-legalization..

ping

May 28 2020, 4:32 PM · Restricted Project
aemerson accepted D80566: GlobalISel: Work on improving stock set of legality predicates.

Seems reasonable.

May 28 2020, 4:32 PM · Restricted Project

May 26 2020

aemerson accepted D80053: [GlobalISel] Don't combine instructions which are fed by memory instructions..

LGTM.

May 26 2020, 5:28 PM · Restricted Project