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Yesterday

karouzakisp added a comment to D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

In D156444#4649111, @craig.topper wrote:

I don't see tests for constantexpr.

Fri, Sep 22, 3:09 PM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

Updated clang-format and fixed minor errors.

Fri, Sep 22, 2:45 PM · Restricted Project, Restricted Project

Mon, Sep 18

karouzakisp added a comment to D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

In D156444#4633397, @karouzakisp wrote:

In D156444#4632536, @craig.topper wrote:

In D156444#4632497, @karouzakisp wrote:

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

"
Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

I don't think we need to mention RISC-V. I've seen cases where the middle end needs this information. This issue https://discourse.llvm.org/t/aggressive-conversion-of-sext-to-zext-blocks-indvarsimplify/61561 was independent of RISC-V.

Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

Mon, Sep 18, 11:05 PM · Restricted Project, Restricted Project

Mon, Sep 4

karouzakisp updated the diff for D156449: [LLVM][Transforms] Zext flag in various optimization passes for RISC-V.

Added nneg flag in InstCombine::visitZExt. Also Added nneg flag in CorrelatedValuePropagation::processZExt.

Mon, Sep 4, 1:24 AM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156442: [RISCV][Backend] Zext flag conversion in RISC-V Backend.

Removed IsKnownNonNegative from RISCVCodeGen and added in InstCombine::visitZExt

Mon, Sep 4, 1:16 AM · Restricted Project, Restricted Project

Fri, Sep 1

karouzakisp updated the diff for D156442: [RISCV][Backend] Zext flag conversion in RISC-V Backend.

Fixed the test that failed to convert the zext(value) to sext(value) whenever the value was assumed to be non negative by llvm.assume

Fri, Sep 1, 12:35 AM · Restricted Project, Restricted Project

Thu, Aug 31

karouzakisp added a comment to D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

In D156444#4632536, @craig.topper wrote:

In D156444#4632497, @karouzakisp wrote:

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

"
Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.
This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
and it is always cheaper than performing a zero extension .

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8

I don't think we need to mention RISC-V. I've seen cases where the middle end needs this information. This issue https://discourse.llvm.org/t/aggressive-conversion-of-sext-to-zext-blocks-indvarsimplify/61561 was independent of RISC-V.

Thu, Aug 31, 10:59 PM · Restricted Project, Restricted Project

karouzakisp added a comment to D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

In D156444#4624088, @nikic wrote:

This is still missing LangRef changes.

I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.

Thu, Aug 31, 2:04 PM · Restricted Project, Restricted Project

Tue, Aug 29

karouzakisp updated the diff for D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

Removed more redudant white spaces.

Tue, Aug 29, 6:13 AM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

Removed redudant whitespaces.

Tue, Aug 29, 4:03 AM · Restricted Project, Restricted Project

Mon, Aug 28

karouzakisp updated the diff for D156442: [RISCV][Backend] Zext flag conversion in RISC-V Backend.

Added simple tests.

Mon, Aug 28, 1:59 PM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

Changed flag's name from `was_sext to nneg`. Updated the LangRef and all the required changes such as Instruction.h Operator.h.

Mon, Aug 28, 1:57 PM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156449: [LLVM][Transforms] Zext flag in various optimization passes for RISC-V.

Removed some redudant and inappropriate settings of the flag in the Transforms. Also updated the transforms calling method name from setWasSext to setNonNeg to set the flag.

Mon, Aug 28, 1:45 PM · Restricted Project, Restricted Project

Jul 27 2023

karouzakisp retitled D156449: [LLVM][Transforms] Zext flag in various optimization passes for RISC-V from Zext flag in various optimization passes for RISC-V to [LLVM][Transforms] Zext flag in various optimization passes for RISC-V.

Jul 27 2023, 10:10 AM · Restricted Project, Restricted Project

karouzakisp retitled D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V from Zext flag in IR for RISC-V to [llvm][RISCV][IR] Zext flag in IR for RISC-V.

Jul 27 2023, 10:09 AM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156442: [RISCV][Backend] Zext flag conversion in RISC-V Backend.

Added -U999999 in
git show
to make possible the reviewing via the web interface.

Jul 27 2023, 10:08 AM · Restricted Project, Restricted Project

karouzakisp retitled D156442: [RISCV][Backend] Zext flag conversion in RISC-V Backend from Zext flag conversion in RISC-V Backend to [RISCV][Backend] Zext flag conversion in RISC-V Backend.

Jul 27 2023, 10:06 AM · Restricted Project, Restricted Project

karouzakisp set the repository for D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V to rG LLVM Github Monorepo.

Jul 27 2023, 10:04 AM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156449: [LLVM][Transforms] Zext flag in various optimization passes for RISC-V.

Added -U999999 in
git show
to make possible the reviewing via the web interface.

Jul 27 2023, 10:04 AM · Restricted Project, Restricted Project

karouzakisp updated the diff for D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V.

Added -U999999 in
git show
to make the reviewing possible via the web interface

Jul 27 2023, 10:02 AM · Restricted Project, Restricted Project

karouzakisp retitled D156442: [RISCV][Backend] Zext flag conversion in RISC-V Backend from [llvm][RISCV][Backend] to Zext flag conversion in RISC-V Backend.

Jul 27 2023, 9:49 AM · Restricted Project, Restricted Project

karouzakisp retitled D156449: [LLVM][Transforms] Zext flag in various optimization passes for RISC-V from [LLVM][Transforms] to Zext flag in various optimization passes for RISC-V.