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Feb 3 2023

marksl accepted D143252: [CodeGen] Make more use of MachineOperand::getOperandNo. NFC..

LGTM

Feb 3 2023, 10:07 AM · Restricted Project, Restricted Project

Oct 29 2021

marksl added inline comments to D112264: [ARC] Upstream the Synopsys out-of-tree load/store increment pass.
Oct 29 2021, 1:07 PM · Restricted Project
marksl updated the diff for D112264: [ARC] Upstream the Synopsys out-of-tree load/store increment pass.

Addressed the issues raised by Graham Yiu regarding Synopsys specific bug report numbers and release versions in comments

Oct 29 2021, 1:05 PM · Restricted Project

Oct 21 2021

marksl requested review of D112264: [ARC] Upstream the Synopsys out-of-tree load/store increment pass.
Oct 21 2021, 12:52 PM · Restricted Project

Oct 7 2021

marksl committed rG417f8ea4baba: [ARC] ARCRegisterInfo cleanup prior to adding core register pairs (ARC32) and… (authored by marksl).
[ARC] ARCRegisterInfo cleanup prior to adding core register pairs (ARC32) and…
Oct 7 2021, 1:03 PM
marksl committed rG20c074ee969d: C] Add option to ARCOptAddrMode to disable the pass and diagnose errors (authored by marksl).
C] Add option to ARCOptAddrMode to disable the pass and diagnose errors
Oct 7 2021, 9:08 AM
marksl closed D111255: [ARC] Add option to ARCOptAddrMode to disable the pass and diagnose errors.
Oct 7 2021, 9:08 AM · Restricted Project

Oct 6 2021

marksl requested review of D111255: [ARC] Add option to ARCOptAddrMode to disable the pass and diagnose errors.
Oct 6 2021, 12:01 PM · Restricted Project

Oct 4 2021

marksl requested review of D111084: [ARC] ARCRegisterInfo cleanup prior to adding core register pairs (ARC32) and 64-bit core registers (ARC64).
Oct 4 2021, 11:41 AM · Restricted Project

Sep 10 2021

marksl committed rG7c82db3634c1: [ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE (authored by marksl).
[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE
Sep 10 2021, 1:05 PM
marksl closed D109615: [ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE.
Sep 10 2021, 1:05 PM · Restricted Project
marksl requested review of D109615: [ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE.
Sep 10 2021, 10:45 AM · Restricted Project

Aug 25 2021

marksl committed rG8c3886b0ec98: [ARC] Add ADC (addition with carry) and SBC (subtraction with carry)… (authored by thomasjohns).
[ARC] Add ADC (addition with carry) and SBC (subtraction with carry)…
Aug 25 2021, 7:47 AM
marksl closed D108672: [ARC] Add ADC (addition with carry) and SBC (subtraction with carry) instructions.
Aug 25 2021, 7:47 AM · Restricted Project
marksl accepted D108672: [ARC] Add ADC (addition with carry) and SBC (subtraction with carry) instructions.

Looks good

Aug 25 2021, 6:55 AM · Restricted Project

Aug 24 2021

marksl committed rGce1dc9d647a7: [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for… (authored by thomasjohns).
[ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for…
Aug 24 2021, 11:55 AM
marksl closed D108598: [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions.
Aug 24 2021, 11:54 AM · Restricted Project
marksl accepted D108598: [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions.

Looks good

Aug 24 2021, 10:25 AM · Restricted Project
marksl requested changes to D108598: [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions.
Aug 24 2021, 8:31 AM · Restricted Project

Aug 10 2021

marksl committed rGb82108687689: [ARC] Add codegen for count trailing zeros intrinsic for the ARC backend (authored by thomasjohns).
[ARC] Add codegen for count trailing zeros intrinsic for the ARC backend
Aug 10 2021, 12:09 PM
marksl closed D107828: [ARC] Add codegen for count trailing zeros intrinsic for the ARC backend.
Aug 10 2021, 12:09 PM · Restricted Project
marksl accepted D107828: [ARC] Add codegen for count trailing zeros intrinsic for the ARC backend.

Thanks for fixing the clang-tidy issue

Aug 10 2021, 9:57 AM · Restricted Project
marksl accepted D107828: [ARC] Add codegen for count trailing zeros intrinsic for the ARC backend.

Looks good

Aug 10 2021, 8:13 AM · Restricted Project

Aug 6 2021

marksl committed rGf8a449514931: [ARC] Add codegen for llvm.ctlz intrinsic for the ARC backend (authored by thomasjohns).
[ARC] Add codegen for llvm.ctlz intrinsic for the ARC backend
Aug 6 2021, 12:20 PM
marksl accepted D107611: [ARC] Add codegen for llvm.ctlz intrinsic for the ARC backend.

Looks good

Aug 6 2021, 11:36 AM · Restricted Project, Restricted Project
marksl added inline comments to D107611: [ARC] Add codegen for llvm.ctlz intrinsic for the ARC backend.
Aug 6 2021, 8:59 AM · Restricted Project, Restricted Project

Jul 29 2021

marksl committed rGe622c99f305d: [ARC] Add norm/normh instructions with disassembly tests (authored by marksl).
[ARC] Add norm/normh instructions with disassembly tests
Jul 29 2021, 5:56 PM
marksl requested review of D107118: [ARC] Add norm/normh instructions with disassembly tests.
Jul 29 2021, 4:59 PM · Restricted Project
marksl committed rGcc238a6e0388: [ARC] Add additional mov immediate instruction formats with a fix for u6… (authored by thomasjohns).
[ARC] Add additional mov immediate instruction formats with a fix for u6…
Jul 29 2021, 4:46 PM
marksl closed D107088: [ARC] Add additional mov immediate instruction formats with a fix for u6 decoding.
Jul 29 2021, 4:46 PM · Restricted Project
marksl accepted D107088: [ARC] Add additional mov immediate instruction formats with a fix for u6 decoding.

Looks good to me

Jul 29 2021, 1:53 PM · Restricted Project
marksl added inline comments to D107088: [ARC] Add additional mov immediate instruction formats with a fix for u6 decoding.
Jul 29 2021, 11:54 AM · Restricted Project

Jul 22 2021

marksl committed rG51d8e67e88d1: [ARC] Add tablegen definition for the Find Leading Set (FLS) instruction (authored by thomasjohns).
[ARC] Add tablegen definition for the Find Leading Set (FLS) instruction
Jul 22 2021, 5:45 PM
marksl closed D106602: Add tablegen definition for the Find Leading Set (FLS) instruction for the ARC backend.
Jul 22 2021, 5:45 PM · Restricted Project
marksl accepted D106602: Add tablegen definition for the Find Leading Set (FLS) instruction for the ARC backend.

Your changes look good to me

Jul 22 2021, 3:23 PM · Restricted Project
marksl committed rG1cda1e618648: [ARC] Add disassembly for the conditioned RSUB immediate instruction (authored by thomasjohns).
[ARC] Add disassembly for the conditioned RSUB immediate instruction
Jul 22 2021, 11:36 AM
marksl closed D106497: Add disassembly for the conditioned RSUB immediate instruction for the ARC backend.
Jul 22 2021, 11:35 AM · Restricted Project
marksl accepted D106497: Add disassembly for the conditioned RSUB immediate instruction for the ARC backend.
Jul 22 2021, 10:39 AM · Restricted Project

Jul 21 2021

marksl added inline comments to D106497: Add disassembly for the conditioned RSUB immediate instruction for the ARC backend.
Jul 21 2021, 3:27 PM · Restricted Project
marksl added inline comments to D106497: Add disassembly for the conditioned RSUB immediate instruction for the ARC backend.
Jul 21 2021, 3:01 PM · Restricted Project

Jul 12 2021

marksl committed rG6b3eba7c285c: [ARC] Add disassembly for the conditioned move immediate instruction (authored by thomasjohns).
[ARC] Add disassembly for the conditioned move immediate instruction
Jul 12 2021, 12:37 PM
marksl closed D105560: Add disassembly for the conditioned move immediate instruction for the ARC backend.
Jul 12 2021, 12:37 PM · Restricted Project

Jul 8 2021

marksl accepted D105560: Add disassembly for the conditioned move immediate instruction for the ARC backend.

Your change looks good to me

Jul 8 2021, 9:12 AM · Restricted Project

Jul 7 2021

marksl added a comment to D105560: Add disassembly for the conditioned move immediate instruction for the ARC backend.

Could you fix the issues reported by clang-tidy?

Jul 7 2021, 12:00 PM · Restricted Project

Jun 18 2021

marksl accepted D104558: Add norm sub-target feature to table gen for ARC.

Looks fine to me

Jun 18 2021, 11:23 AM · Restricted Project

Jun 3 2021

marksl requested review of D103653: Add commutable attribute to opcodes for ARC.
Jun 3 2021, 3:32 PM · Restricted Project

Oct 14 2020

marksl added inline comments to D88907: Polly - specify address space when creating a pointer to a vector type.
Oct 14 2020, 7:44 AM · Restricted Project, Restricted Project

Oct 7 2020

marksl updated the diff for D88907: Polly - specify address space when creating a pointer to a vector type.

Reduced the arguments to opt

Oct 7 2020, 12:23 PM · Restricted Project, Restricted Project

Oct 6 2020

marksl requested review of D88907: Polly - specify address space when creating a pointer to a vector type.
Oct 6 2020, 8:53 AM · Restricted Project, Restricted Project

Mar 26 2020

marksl added a comment to D68510: [PATCH 16/27] [noalias] Clone scopes and llvm.noalias.decl when unrolling..

I assume that a similar fix would then be necessary for loop peeling (and any such loop optimization that clones blocks).

Mar 26 2020, 3:14 PM · Restricted Project

Feb 25 2019

marksl created D58629: Inlining Entry/Exit Instrumentation.
Feb 25 2019, 8:38 AM · Restricted Project

Apr 19 2017

marksl abandoned D32240: InstCombineCast AShr transformation.

This does not appear to be an issue on the trunk.

Apr 19 2017, 4:28 PM
marksl updated the diff for D32240: InstCombineCast AShr transformation.

Now with transform and test case.

Apr 19 2017, 3:09 PM
marksl updated the diff for D32240: InstCombineCast AShr transformation.

Added test case

Apr 19 2017, 3:06 PM
marksl updated the diff for D32240: InstCombineCast AShr transformation.
Apr 19 2017, 2:54 PM
marksl created D32240: InstCombineCast AShr transformation.
Apr 19 2017, 12:43 PM

Jun 16 2016

marksl added a comment to D16829: An implementation of Swing Modulo Scheduling.

After ISEL our compare instructions, multiply, and MAC instructions have real physical register side effects. I'm getting errors from SWP for loops containing these physical register dependencies. Are you aware of this? Is there a way to model physical register dependencies with loop carried dependencies such that we would generate correct code for them?

Jun 16 2016, 11:23 AM

Apr 22 2016

marksl updated the diff for D19239: Modified MachinePipeliner http://reviews.llvm.org/D16829.

This version of MachinePipeliner.cpp contains several fixes. Please search for SYNOPSYS for my changes to Brendon's original source.

Apr 22 2016, 4:08 PM · Restricted Project

Apr 18 2016

marksl retitled D19239: Modified MachinePipeliner http://reviews.llvm.org/D16829 from to Modified MachinePipeliner http://reviews.llvm.org/D16829.
Apr 18 2016, 2:38 PM · Restricted Project

Mar 9 2016

marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 9 2016, 1:43 PM

Mar 1 2016

marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 1 2016, 9:08 AM
marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Mar 1 2016, 7:58 AM

Feb 12 2016

marksl accepted D16829: An implementation of Swing Modulo Scheduling.

Very nice work Brandon.

Feb 12 2016, 4:39 PM

Feb 11 2016

marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 11 2016, 4:59 PM
marksl added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 11 2016, 9:59 AM

Feb 5 2016

marksl added a comment to D16829: An implementation of Swing Modulo Scheduling.

If you have a functional unit that issues in stages such that another instruction of needing the same FU can ussue the very next cycle, then isn't the sum of the cycles too great? Example:

Feb 5 2016, 2:24 PM