Thanks for the review @paquette. I'll update the diff addressing your nit when I push the patch

These are combines which seem generally beneficial (not architecture specific) from the closed source backend I work on. They are beneficial for our backend, so we have been upstreaming these combines to improve GISel.

Patch has been split up into sub-patches, closing this revision:

• https://reviews.llvm.org/D126008
• https://reviews.llvm.org/D126006
• https://reviews.llvm.org/D126005

Updates:

• Removed G_ADD(x, -cst) -> G_SUB(x, cst)
• Very minor NFC addressing https://reviews.llvm.org/D125819#inline-1207969

I'll remove that combine as well. If there's more discussion and it's found to be beneficial then I can open another revision for it.

Sure thing. I'll split this up into separate patches.

Good point about using mi_match, updated the diff.

Updates:

• Rebased patch
• Removed G_ADD(x, y) -> G_OR(x, y) combine
• Exchanged my custom applyAddSubSameReg function for replaceSingleDefInstWithReg
• Add @aemerson and @foad to reviewers list

Thanks for reviews and feedback @arsenm and @foad

Updates:

• Fixed spelling of propagate
• Exchanged my custom apply function for replaceSingleDefInstWithOperand

Forgot to link the differential before pushing, but latest update is in a11489ae3e36063c64921439cbab89d1f3280f4a

Update:

• Added isConvergent check in ProcessBlockPRE

Following Roman's suggestions, the update:

• Move the code preventing CSE of isConvergent instrs into ProcessBlockCSE from isProfitableToCSE
• Adds comments in MachineCSE and the test explaining why isConvergent is checked to prevent CSE
• Adds comment in the test explaining the test is not reproducing an AMDGPU backend bug, but rather is a coverage test for the MachineCSE change

Update: changed basic block checks from CHECK-LABEL to CHECK

Ah ok, good to know. Thanks for the review! Changing them to CHECK.

Update: added handwritten MIR unit test for the MachineCSE change using AMDGPU's DS_SWIZZLE_B32 instr (which is marked isConvergent in llvm/lib/Target/AMDGPU/DSInstructions.td)

Good catch!

Will take a look at this one on Monday (March 1)

I have a fixup ready with the G_FMUL(x, -1.0)->G_FSUB(-0.0, x) change. However, I just want to know in specific terms if there's anything else blocking approval.

I can remove the G_ADD(x, y)->G_OR(x, y) combine if that's a blocker. Let me know if there's anything else specifically blocking the approval of this patch.

Renamed binop_right_to_fp_zero to fmul_by_zero

• Changed G_ADD(x, -cst) -> G_SUB(x, cst) to use APInt
• Added vector and s128 test cases (though some combines don't fire with these input types)

In D87936#2282772, @tschuett wrote:

Out of curiosity, is the first rule a win or canonicalisation?

• Changed G_FMUL(x, -1.0) to fold into G_FSUB(0.0, x)
• Fixed clang-tidy warnings
• Changed some fp constants in comments from {n} to {n}.0

I can't take credit for that. It was @hliao who committed the fix (thanks btw!).

Committed in c4e589b7954

• Rebased and fixed merge conflicts
• Removed unnecessary type checks in constantFoldFpUnary
• Removed G_FPTRUNC special case for S64 in constantFoldFpUnary

Thanks again Aditya! I'll reach out to Chris about commit access.

Thanks for the review. Still don't have commit access, will need someone to commit on my behalf. Thanks in advance!

• Changed mul_by_one to right_identity_one
• Changed mul_by_neg_one to use matchConstantOp

• Rebased and fixed merge conflicts

Thanks Aditya!

Thanks for the review. Still don't have commit access, will need someone to commit on my behalf. Thanks in advance!

• Used replaceRegWith instead of building a copy

• Collapsed the many combine rules into a single combine rule with a list of matchable opcodes
• Made the default switch case in constantFoldFpUnary be llvm_unreachable

• Added LLT helper function to get float semantic from scalar LLT (IEEE fp semantics only at the moment)
• Updated constantFoldFpUnary to use the new helper function
• Rebased / fixed merge conflicts

• Rebased and fixed merge conflicts
• Changed setInstr to setInstrAndDebugLoc

It was conflicted until the rebase update, so I doubt it was committed. Thanks for committing this!

• Rebased and resolved conflicts
• Fixed test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir to continue testing unmerge with same regs

• match / apply functions use Optional<APFloat> to pass info about the constant FP.
• Updated rounding modes to be rmNearestTiesToEven
• Refactored constantFoldFpUnary

Rebased and resolved conflicts with new changes to Combine.td.

Fixed clang-tidy feedback
(not enough)

Thanks for the reviews. I don't have commit access, would be appreciated if someone could commit on my behalf. Thanks!

Thanks, Aditya!

Great, thanks for the review! I don't have commit access. Would be great if someone could commit on my behalf.

Moved the two new combiner rules to identity_combines.

Removed the combine for undef selectee value. Will open a separate patch to track that work.

Maybe? It's unclear to me what makes a ConstantExpr poison in the first place, and how combining with it would result in incorrect code (...new hire rolling through).

Looks like my local build wasn't building all the targets (sorry, fixed now). The AMDGPU test failed as a result of moving the existing select_same_val combiner out of the identity_combines group. The diff update moves select_same_val back to identity_combines group. The update does not address @arsenm's comment (waiting on feedback from @craig.topper).

Hey Nicolas, just add some thoughts on this patch.

Looks like a good helper class. Just some minor nits. (haven't looked into the tests just yet)