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Thu, May 28

asb added a comment to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

Sorry for the delay on this - the lockdown situation is really hurting my review time, though it looks like my childcare situation will improve from the week after next.

Thu, May 28, 7:34 AM · Restricted Project

Tue, May 19

asb added inline comments to D79141: [RISCV] Better Split Stack Pointer Adjustment for RVC.
Tue, May 19, 1:03 AM · Restricted Project

Thu, May 14

asb accepted D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64 .

Good catch, thanks for the fix! The logic was incorrectly written assuming isFloatingType would return false for complex values which is of course incorrect.

Thu, May 14, 3:10 AM · Restricted Project
asb added a comment to D78545: [RISCV] Make CanLowerReturn protected for downstream maintenance.

Please check D79928 which cleans up the visibility of all of these overridden methods.

Thu, May 14, 2:38 AM · Restricted Project
asb created D79928: [RISCV] Make visibility of overridden methods in RISCVISelLowering match the parent.
Thu, May 14, 2:38 AM · Restricted Project
asb added a comment to D79492: [RISCV] Improve constant materialization.

I'm in favour of merging a patch that is functionally correct and makes incremental improvements. I'd rather avoid any regression in codesize though if possible. How feasible would it to be to avoid that case? It may be worthwhile leaving some of the materialisation improvements for a follow-up patch in order to land the clear wins now.

Thu, May 14, 2:05 AM · Restricted Project

Tue, May 12

asb accepted D79635: [RISCV] Split the pseudo instruction splitting pass.

Thanks, this looks good to me. PreSched2 is logically a better place for the standard pseudo expansions, though I'm not seeing any codegen changes at all with e.g. the GCC torture suite. But I'm happy to land this as-is.

Tue, May 12, 12:30 AM · Restricted Project
asb added a comment to D79690: [RISCV] Fold ADDIs into load/stores with nonzero offsets.

Could you rebase please? This isn't applying cleanly for me on current master.

Tue, May 12, 12:30 AM · Restricted Project

Mon, May 11

asb added a comment to D78545: [RISCV] Make CanLowerReturn protected for downstream maintenance.

Looks like this landed while I was composing the below:

Mon, May 11, 11:25 PM · Restricted Project

Thu, May 7

asb added a comment to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Hi Paolo. I'm sorry this has been left hanging for some time. On the one hand, with this being an experimental feature and purely additive the bar for merging is slightly lower than e.g. a rewrite of all our existing codegen patterns (which could cause new regressions). On the other hand, this pre-commit review is realistically going to be the time when the codegen patterns and associated tests get most scrutiny and it would be a shame to skip that.

Thu, May 7, 6:12 AM · Restricted Project

Wed, May 6

asb added a comment to D79492: [RISCV] Improve constant materialization.

Thanks, this is a good improvement. Two thoughts, mainly for discussion rather than blocking issues:

Wed, May 6, 11:59 PM · Restricted Project
asb requested changes to D79141: [RISCV] Better Split Stack Pointer Adjustment for RVC.

Thanks Sam. I left a few minor comments inline. From looking at the diff in compiler output on the GCC torture suite, I do see a few cases where there is a potential regression. e.g. loop-ivopts-2.c, which represents a case where the stack adjustment is large, but doesn't overflow the 12-bit immediate fields of addi and s[d|w]. The prologue and epilogue are both two instructions and become three instructions with this patch (although it is a code size win).

Wed, May 6, 11:59 PM · Restricted Project
asb added a comment to D79521: [RISCV] Add SiFive's interrupt modes.

Just to understand the current status with respect to GCC, am I right that support for these attributes is not in upstream GCC? @kito-cheng is there any plan to upstream?

Wed, May 6, 11:15 PM · Restricted Project
asb accepted D79523: [RISCV] Support Constant Pools in Load/Store Peephole.

LGTM, thanks. Left an inline comment pointing out a TODO that can now be removed thanks to this.

Wed, May 6, 10:42 PM · Restricted Project

Tue, May 5

asb accepted D78764: [RISCV] Update debug scratch register names.

LGTM, thanks. Left one tiny nit inline.

Tue, May 5, 8:03 AM · Restricted Project

Apr 30 2020

asb added inline comments to D78905: [RISCV][NFC] Tests for indirect float conversion.
Apr 30 2020, 4:43 AM · Restricted Project
asb added a comment to D78907: [RISCV][NFC] Add tests for checking isnan patterns.
In D78907#2012344, @asb wrote:

LGTM. Minor nit: using %0 and %2 as the only two named values seems odd though? Most other tests in test/CodeGen/RISCV use a/b/... for arguments and %0/%1/%2/... in the body.

I generated the testcases in Clang (actually using godbolt, but it's doing the same IR lowering as clang HEAD is), which is why the arguments don't have names. I can re-introduce them if that's easier.

Apr 30 2020, 4:43 AM · Restricted Project
asb accepted D78907: [RISCV][NFC] Add tests for checking isnan patterns.

LGTM. Minor nit: using %0 and %2 as the only two named values seems odd though? Most other tests in test/CodeGen/RISCV use a/b/... for arguments and %0/%1/%2/... in the body.

Apr 30 2020, 3:37 AM · Restricted Project
asb accepted D78908: [RISCV] Add patterns for checking isnan.

LGTM, thanks!

Apr 30 2020, 3:37 AM · Restricted Project
asb added inline comments to D78908: [RISCV] Add patterns for checking isnan.
Apr 30 2020, 2:25 AM · Restricted Project
asb added inline comments to D78906: [RISCV] Add patterns for indirect float conversions.
Apr 30 2020, 2:25 AM · Restricted Project
asb added inline comments to D78905: [RISCV][NFC] Tests for indirect float conversion.
Apr 30 2020, 2:25 AM · Restricted Project
asb added a comment to D78764: [RISCV] Update debug scratch register names.

Sorry to ask you to move things back, but I think the debug CSR tests would make most sense in machine-csr-names.s on the basis that the privileged spec does list those CSRs in the "machine-level CSR names" table.

Apr 30 2020, 1:12 AM · Restricted Project
asb updated the diff for D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths.

Updated patch to include full context.

Apr 30 2020, 1:12 AM · Restricted Project
asb updated subscribers of D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths.
Apr 30 2020, 12:34 AM · Restricted Project
asb created D79155: [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths.
Apr 30 2020, 12:34 AM · Restricted Project

Apr 23 2020

asb added a comment to D78583: [RISCV] Add instruction definition for dret.

Thanks for the patch, as we discussed last week I think supporting dret with the same ease as the privileged instructions is the right path. Given dret is defined in the debug spec rather than the privileged spec, could you please:

  • Move the test to a new test file debug-valid.s
  • Move the DRET instruction definition to a new section of RISCVInstrInfo.td with an internal header like
//===----------------------------------------------------------------------===//
// Debug instructions
//===----------------------------------------------------------------------===//
Apr 23 2020, 8:04 AM · Restricted Project

Apr 9 2020

asb added a comment to D73891: [RISCV] Support experimental/unratified extensions.

I've approved D65649 now, so I think this one can land as soon as that one does.

Apr 9 2020, 8:07 AM · Restricted Project
asb accepted D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

I think we should land this and continue further development in-tree. There might be a few minor refactorings I want to propose after the fact, but these shouldn't block this going forwards.

Apr 9 2020, 7:34 AM · Restricted Project
asb added a comment to D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive.

I can see the argument for changing the default of EnableRVCHintInstrs. Might we be better just doing that, and keeping it as "rvc-hints" to avoid adding negative features?

Apr 9 2020, 5:55 AM · Restricted Project
asb accepted D77567: [RISCV] Implement evaluateBranch.

Thanks Simon, LGTM. I noted a tiny nit re the test file.

Apr 9 2020, 5:55 AM · Restricted Project

Mar 26 2020

asb added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

I agree, it seems more like a sketch of what they should be, but the mentioning of the size improvements suggested to me perhaps they should be, since evaluating the potential "what the final B extension should look like" it probably should be included. There is the question of where this should be enabled, my first thought (which this patch implements) is Zbb because it seemed the most logical, but maybe given the instructions stated state does another subextension make sense for its evaluation? These are all experimental so I think there's some leeway to some option, but I think it would be good to land it if we think people may be using it/want to evaluate it. I suspect there's many valid routes with this being experimental, we just need to choose one we have concensus around making sense. Perhaps a topic for today's call?

Mar 26 2020, 8:38 AM · Restricted Project
asb added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

Submitting the comments I have so far - need to continue going through in more detail.

Mar 26 2020, 8:38 AM · Restricted Project
asb accepted D76767: [RISCV] Support negative constants in CompressInstEmitter.

This is a much simpler fix! Looks good to me.

Mar 26 2020, 8:06 AM · Restricted Project
asb added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

I'm reviewing this with an eye to merging it, but one big thing that comes to mind is the compressed instructions. The draft bitmanip spec describes these under "Future compressed instructions" and says "It presumably would make sense for a future revision of the “C” extension to include compressed opcodes for those instructions." My reading is that this is more of a sketch of potential encodings and a less firm proposal than the 32-bit encodings described elsewhere in the spec. Do you disagree with that assessment?

Mar 26 2020, 7:33 AM · Restricted Project
asb added a comment to D76828: [RISC-V] Support __builtin_thread_pointer .

Thanks for the patch. I added a couple of nits - please rename the test file to thread-pointer.ll to match what other backends do and make it more discoverable. Also, although there different is minor we do use update_llc_test_checks.py for essentially all RISC-V tests so it would be good to use that for thread-pointer.ll as well.

Mar 26 2020, 7:00 AM · Restricted Project
asb added a comment to D76767: [RISCV] Support negative constants in CompressInstEmitter.

I was thinking about making it clearer why this cast is necessary. The first thought was obviously to add a comment to explain (similar to the comment in your review description). But maybe there's an argument for adding a small helper? Although it would literally just be doing a cast, it's name and description should make it much clearer what is going on. I don't feel super strongly about that approach though - so do speak up if you disagree!

Mar 26 2020, 5:55 AM · Restricted Project
asb accepted D75168: [sanitizer][RISCV] Implement SignalContext::GetWriteFlag for RISC-V.

This LGTM, thanks Luis!

Mar 26 2020, 5:23 AM · Restricted Project, Restricted Project

Mar 19 2020

asb added a comment to D75168: [sanitizer][RISCV] Implement SignalContext::GetWriteFlag for RISC-V.
In D75168#1907941, @asb wrote:

There are some cases where you need to perform more checking in order to be future proof for possible new standard extensions. Specifically, review the RVC Instruction Set Listings in the RISC-V spec and check for where an encoding is marked as "RES" (reserved). e.g. C.LWSP is valid only if rd!=0, and the version with rd=0 is a reserved encoding. Similar with C.LDSP. I think it's just those two.

I'm not sure that's something we want to do. Those are reserved for HINT instructions. The spec says:

This HINT encoding has been chosen so that simple implementations can ignore HINTs alto-
gether, and instead execute a HINT as a regular computational instruction that happens not to
mutate the architectural state.

If the core truly supports those HINTs then it shouldn't trap. If we are trapping presumably it's because the core is just executing the HINT as a plain load/store. That would typically be a NOP, but the address must be invalid and so we are trapping. In that case we are correctly identifying it as a READ or WRITE.

Mar 19 2020, 6:59 AM · Restricted Project, Restricted Project
asb added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

This is starting to look good. I've checked all the encodings, and other than c.zext.w having the wrong value all the encodings are right.

One thing I would consider is to make reviewing/future changes easier, I would define all the instructions in the order they appear in the Chapter 2.11 Opcode Encodings tables. This way, it will be easier to see for future revisions what has changed and make sure the encodings are up to date. This might end up with a few more let Predicates = directives, but we can rearrange and tidy this up when it is all ratified.

Mar 19 2020, 6:59 AM · Restricted Project
asb accepted D73891: [RISCV] Support experimental/unratified extensions.

LGTM, thanks Simon!

Mar 19 2020, 6:27 AM · Restricted Project

Mar 5 2020

asb added a comment to D75168: [sanitizer][RISCV] Implement SignalContext::GetWriteFlag for RISC-V.

There are some cases where you need to perform more checking in order to be future proof for possible new standard extensions. Specifically, review the RVC Instruction Set Listings in the RISC-V spec and check for where an encoding is marked as "RES" (reserved). e.g. C.LWSP is valid only if rd!=0, and the version with rd=0 is a reserved encoding. Similar with C.LDSP. I think it's just those two.

Mar 5 2020, 9:50 AM · Restricted Project, Restricted Project
asb accepted D75522: [compiler-rt][builtins][RISCV] Port __clear_cache to RISC-V Linux.

LGTM, thanks!

Mar 5 2020, 8:13 AM · Restricted Project, Restricted Project

Feb 27 2020

asb added a comment to D75099: [AVR] Include AVR by default in LLVM builds.

Hi Dylan - on the mailing list thread for this I raised a concern about disassembler support based on comments I'd seen in a recent patch. Can you please clarify the current status there?

Feb 27 2020, 5:22 AM · Restricted Project

Feb 20 2020

asb added a comment to D74453: [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG.

Yes, if @jrtc27 commits I'd be supportive of a cherry-pick to the release branch.

Feb 20 2020, 7:53 AM · Restricted Project
asb added a comment to D68964: cmake/modules/CheckAtomic.cmake: catch false positives in RISC-V.

Yes, please backport (if possible) all other related changes mentioned above (if they are not yet part of 10.0).

This would help distributions to avoid hacking LDFLAGS / build systems files while building LLVM/Clang stack on Linux.

Feb 20 2020, 7:53 AM · Restricted Project
asb updated subscribers of D74596: [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler.

@hans this patch fixes a reported bug https://bugs.llvm.org/show_bug.cgi?id=42984 and is non-invasive. I'd be in favour of cherry-picking for 10.0 if you're ok with that.

Feb 20 2020, 5:55 AM · Restricted Project
asb accepted D74453: [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG.

Great fix, thanks @jrtc27. Please do go ahead and commit.

Feb 20 2020, 5:28 AM · Restricted Project

Feb 19 2020

asb added a comment to D68964: cmake/modules/CheckAtomic.cmake: catch false positives in RISC-V.

CC @hans for 10.0

+asb from code_owners.txt, what do you think?

Feb 19 2020, 9:31 AM · Restricted Project

Feb 6 2020

asb added a comment to D74022: [ELF][RISCV] Add R_RISCV_IRELATIVE.

Thanks for implementing this - I'd personally like to see the psABI proposal https://github.com/riscv/riscv-elf-psabi-doc/pull/131 merged before merging into LLVM/LLD.

Feb 6 2020, 5:32 AM · Restricted Project

Jan 23 2020

asb added a comment to D71820: [lld][RISCV] Print error when encountering R_RISCV_ALIGN.

@MaskRay, @ruiu, would you be in favour of this being backported to 10.0?

Jan 23 2020, 5:53 AM · Restricted Project
asb added a comment to D73211: [RISCV] Fix evaluating %pcrel_lo against global and weak symbols.

I've filed a request to merge this into the release branch here https://bugs.llvm.org/show_bug.cgi?id=44631 - thanks for the fix James!

Jan 23 2020, 5:35 AM · Restricted Project

Jan 14 2020

asb added inline comments to D70837: [RISCV] Support ABI checking with per function target-features.
Jan 14 2020, 6:35 AM · Restricted Project

Jan 13 2020

asb accepted D69590: [RISCV] Fix ILP32D lowering for double+double/double+int return types.

This looks good to me, thanks James. I had a closer step through of the logic here to convince myself.

Jan 13 2020, 5:39 AM · Restricted Project

Jan 10 2020

asb accepted D72471: [RISCV] Check register class for AMO memory operands.

Thanks for the fix! As Sam says, explaining the issue in the commit message would be useful.

Jan 10 2020, 5:36 AM · Restricted Project

Jan 9 2020

asb accepted D67495: [RISCV] Collect Statistics on Compressed Instructions.
Jan 9 2020, 6:27 AM · Restricted Project
asb added a comment to D67495: [RISCV] Collect Statistics on Compressed Instructions.

LGTM. My only concern was if it made sense to use the same statistic to count in both places, and if we could end up double counting the instructions emitted (now, or in a future LLVM version). After a quick look I didn't really see other targets using the same approach, but I also can't think of a way where this ends up actually being problematic.

My understanding is that instructions only go through one of these functions. RISCVAsmParser.cpp is used by the assembler only, and the RISCVAsmPrinter.cpp is only used by LLVM CodeGen. This should mean that instructions are not double-counted (today). Yes I'm not sure why we have both, I think @asb did this to ensure better layering.

Jan 9 2020, 6:27 AM · Restricted Project

Dec 19 2019

asb accepted D71536: [RISCV] Don't crash on unsupported relocations.

LGTM, thanks.

Dec 19 2019, 7:13 AM · Restricted Project

Dec 16 2019

asb requested changes to D71536: [RISCV] Don't crash on unsupported relocations.

Please update the check so it checks the error location too, like we do for other *invalid.s checks.

Dec 16 2019, 6:08 AM · Restricted Project

Dec 12 2019

asb added inline comments to D71101: [lld][RISCV] Use an e_flags of 0 if there are only binary input files..
Dec 12 2019, 5:30 AM · Restricted Project

Dec 5 2019

asb accepted D68290: [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes().

LGTM, thanks!

Dec 5 2019, 8:09 AM · Restricted Project

Nov 21 2019

asb added a comment to D62190: [RISCV] Allow shrink wrapping for RISC-V.

I note that the TargetFrameLowering hooks canUseAsPrologue and canUseAsEpilogue are both called by the shrink wrapper. They default to true, but targets may need to override this for correctness. Looking at e.g. AArch64, I see it overrides canUseAsPrologue and returns false in the case that the function needs stack realignment and there are no scratch registers available. Are you certain that no such case is needed for RISC-V?

Nov 21 2019, 7:39 AM · Restricted Project
asb accepted D70204: [Object][RISCV] Resolve R_RISCV_32_PCREL.

LGTM, thanks Luis.

Nov 21 2019, 4:52 AM · Restricted Project
asb accepted D69899: [RISCV] Improve assembler missing feature warnings.

Thanks Simon, LGTM. I did wonder about just saying e.g. "the 'c' instruction set extension", but on balance I can't see it being any easier to understand or more obvious what to change, and it's handy giving a longer description.

Nov 21 2019, 3:51 AM · Restricted Project
asb added inline comments to D70426: [DAGCombiner][RISCV] Avoid FCOPYSIGN folding of legalizing operand casts.
Nov 21 2019, 3:51 AM · Restricted Project

Nov 15 2019

asb accepted D69894: [RISCV] Add assembly mnemonic spell checking.

Compared this to commits that introduced assembly mnemonic spellchecking for other backends, and it looks good to me. Thanks Simon!

Nov 15 2019, 8:00 AM · Restricted Project

Nov 14 2019

asb accepted D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults.

Please update the commit message to clarify the cases where we do deviate from the GCC defaults, but this looks good to me.

Nov 14 2019, 7:48 AM · Restricted Project

Oct 31 2019

asb added a comment to D69590: [RISCV] Fix ILP32D lowering for double+double/double+int return types.

Thanks James - won't this still leave problems for structs that need flattening?

Oct 31 2019, 6:55 AM · Restricted Project

Oct 24 2019

asb accepted D69390: [RISCV] Lower llvm.trap and llvm.debugtrap.

LGTM, thanks!

Oct 24 2019, 9:34 AM · Restricted Project

Oct 14 2019

asb added a comment to D67185: [RISCV] Add support for -ffixed-xX flags.

Note, D68862 is in-progress at the moment, which is related to this patch.

Oct 14 2019, 9:38 AM · Restricted Project, Restricted Project

Oct 3 2019

asb accepted D68392: [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr).

LGTM, thanks!

Oct 3 2019, 8:13 AM · Restricted Project
asb added a reviewer for D68392: [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr): asb.
Oct 3 2019, 7:23 AM · Restricted Project
asb added a comment to D68392: [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr).

Thanks Ed, could you add some tests to test/MC/RISCV/rvf-aliases-valid.s please?

Oct 3 2019, 7:23 AM · Restricted Project
asb added a comment to D62190: [RISCV] Allow shrink wrapping for RISC-V.

I think this patch is orthogonal to save/restore via libcalls, and we can probably land it sooner. Could you please rebase so it's standalone?

Oct 3 2019, 6:59 AM · Restricted Project
asb added a comment to D66870: [Sanitizers] Add support for RISC-V 64-bit.

@schwab - do you need someone to commit this for you?

Oct 3 2019, 5:58 AM · Restricted Project, Restricted Project
asb added a comment to D68290: [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes().

I like the direction of this, Thanks Ana. Did you look at modifying getInstSizeInBytes? That would benefit other callers beyond the outliner.

Oct 3 2019, 5:52 AM · Restricted Project

Sep 26 2019

asb added a comment to D68060: [RISCV] Materialization of 64-bit mask immediate.

Plus our dev meeting coding lab last year stepped through a similar optimisation, so we really should land it.

Sep 26 2019, 4:51 AM · Restricted Project
asb accepted D67423: [RISCV] Rename FPRs and use Register arithmetic.

This LGTM, thanks. Added a few nits. I think Sam's suggestion of adding a helper function or two to handle the register arithmetic is worth evaluating, but doesn't need to be done in this patch.

Sep 26 2019, 2:44 AM · Restricted Project

Sep 17 2019

asb added a comment to D67423: [RISCV] Rename FPRs and use Register arithmetic.

I'm still personally not fond of the Fx_F/Fx_D convention. The fact that F0_F < F1_F < F0_D < F1_D is highly surprising, especially when F0_32 < F0_64 < F1_32 < F1_64, and not what one would naively assume. I also don't know whether this peculiarity of TableGen is meant to be something that's relied upon. I know it doesn't match the ISA convention of always calling them Fx, but Fx and Dx have precedence in other backends and do not risk this same confusion. Moreover, the spec itself is highly inconsistent in how to refer to single and double precision floating point:

Sep 17 2019, 5:37 AM · Restricted Project

Sep 11 2019

asb committed rL371632: Request commit access for asb.
Request commit access for asb
Sep 11 2019, 8:50 AM

Sep 10 2019

asb accepted D65950: [RISCV] Add Option for Printing Architectural Register Names.

LGTM, thanks!

Sep 10 2019, 8:38 AM · Restricted Project

Aug 29 2019

asb added a comment to D66887: [test-suite] Add GCC C Torture Suite.

Thanks for pushing this forwards Sam. For the RISC-V backend we've been using a downstream shell script for this for ages, and I've always felt it would be better if the torture suite could be used from the LLVM test suite. It's been a while since I went over the excluded tests, it's possible it would benefit from further review if all the masked tests really should be masked.

Aug 29 2019, 3:38 AM · Restricted Project

Aug 27 2019

asb accepted D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics.

LGTM, thanks!

Aug 27 2019, 8:33 AM · Restricted Project, Restricted Project
asb added a comment to D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics.

This LGTM, but given how much discussion there has been about MaxPromoteWidth it would be great to get some test coverage for it.

Aug 27 2019, 6:23 AM · Restricted Project, Restricted Project
asb accepted D66752: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass.

This triggers when building the Linux kernel too. I forgot to submit this patch after getting that working. I also couldn't get a meaningful test case for it that didn't seem like it would be horribly brittle. LGTM, thanks.

Aug 27 2019, 6:23 AM · Restricted Project

Aug 20 2019

asb committed rG7cb3cd34e8d7: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the… (authored by asb).
[RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the…
Aug 20 2019, 5:34 AM
asb committed rL369375: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the….
[RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the…
Aug 20 2019, 5:31 AM
asb closed D66419: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location.
Aug 20 2019, 5:31 AM · Restricted Project
asb added inline comments to D66419: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location.
Aug 20 2019, 5:30 AM · Restricted Project

Aug 19 2019

asb updated the diff for D66419: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location.
Aug 19 2019, 8:12 AM · Restricted Project
asb created D66419: [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location.
Aug 19 2019, 8:04 AM · Restricted Project
asb resigned from D63409: [RISCV] Specify various encodings for DWARF exception handling.

Resigning as a reviewer, as the intent of this change is captured in rL366327.

Aug 19 2019, 6:26 AM · Restricted Project
asb committed rG1c1f8f215d89: [RISCV] Don't force absolute FK_Data_X fixups to relocs (authored by asb).
[RISCV] Don't force absolute FK_Data_X fixups to relocs
Aug 19 2019, 6:23 AM
asb committed rL369257: [RISCV] Don't force absolute FK_Data_X fixups to relocs.
[RISCV] Don't force absolute FK_Data_X fixups to relocs
Aug 19 2019, 6:23 AM
asb closed D63404: [RISCV] Don't force absolute FK_Data_X fixups to relocs.
Aug 19 2019, 6:22 AM · Restricted Project
asb added inline comments to D62592: [RISCV] Add support for RVC HINT instructions.
Aug 19 2019, 5:59 AM · Restricted Project
asb accepted D62592: [RISCV] Add support for RVC HINT instructions.

Looks good to me, thanks! We may later review whether the ability to enable/disable these hints is worth it or not (I know I'd been in favour from the start, but looking at it with fresh eyes I'm not sure it's fully necessary), but this is a useful step forwards.

Aug 19 2019, 5:59 AM · Restricted Project
asb requested changes to D65950: [RISCV] Add Option for Printing Architectural Register Names.

Actually changing my mind. This would be better tested by adopting something like arch-reg-names.s from D66139 (and extending that to handle FP regs), and leaving the inline-asm tests alone (huge increase in test size, which makes them harder to follow). Make that change, and then it looks good to me.

Aug 19 2019, 5:35 AM · Restricted Project
asb accepted D66139: [RISCV] Support llvm-objdump -M no-aliases and -M numeric.

LGTM, but wouldn't it be worth moving arch-reg-names.s to D65950, and also expanding it to handle FP regs?

Aug 19 2019, 5:35 AM · Restricted Project
asb accepted D65950: [RISCV] Add Option for Printing Architectural Register Names.

LGTM, thanks!

Aug 19 2019, 5:30 AM · Restricted Project