Should be fixed by 998118c3d3bd6a394c1da35f7570cce1a3145ea3, which does more checks on alignment.
Thu, Apr 2
Wed, Apr 1
Tue, Mar 31
Mon, Mar 30
Sat, Mar 28
Thu, Mar 26
Address @sfertile 's comment.
Wed, Mar 25
Tue, Mar 24
Sun, Mar 15
Sat, Mar 7
Feb 18 2020
Feb 17 2020
LGTM. Please wait a couple of days to land in case other reviewers have other concerns.
We are combing the instructions into sext_inreg instead of Power specific node SExtVElems, and then, it is selected as hw instruction which is defined in the pattern td.
CMIIW, SExtVElems works on types that fit in a vector register, like v16i8. And according to codes SExtVElems generates, it intends to sext lower bits in-place, which suggests SIGN_EXTEND_INREG.
Feb 13 2020
I believe the conversion of SNaN to QNaN is expected here. Note that the (current) C standard does not mention support signaling NaNs at all, and does not really ever mention them. This is planned to be fixed with the upcoming C2x version, which explicitly states that "rint" is supposed to implement the IEEE-754 "roundToIntegerExact" function. And that function, like most general functions defined by IEEE-754, is indeed defined to return a QNaN when the input is a SNaN.
Thanks for the information.
Feb 12 2020
Is that specified by any doc/spec? Thanks.
Feb 10 2020
Correct me if I'm wrong. rint(x) returns x if x is an NaN. However, intruction like XSRDPIC may turn SNAN to QNAN. Does it matter?
Jan 6 2020
Jan 2 2020
Can you add more info about compilation errors and compiler version?
Dec 30 2019
LGTM. Given some verbosity can really help us to understand code quickly.
Dec 29 2019
LGTM with one nit.
Dec 26 2019
Dec 23 2019
I would suggest to retitle it to be more descriptive about code behavior, like 'Add check' blah blah. Describe what bugs it can fix in summary field.
Dec 22 2019
Dec 18 2019
Dec 17 2019
Dec 16 2019
Add indentation in RUN lines.
Dec 12 2019
Hi @Jim we currently prefer to set this flag at a fine grained granularity, it's the purpose of sending a series of patches to perform such cleanups.
Dec 11 2019
Can you provide tests to demonstrate how ISD::SIGN_EXTEND_INREG works on PowerPC?
Dec 10 2019
Dec 9 2019
@lkail When committing code for others, please follow the format described in Developer Policy. Thanks.
https://llvm.org/docs/DeveloperPolicy.html#attribution-of-changesAttribution of Changes should be in a separate line, after the end of the body, as simple as “Patch by John Doe.”. This is how we officially handle attribution, and there are automated processes that rely on this format.
Dec 6 2019
@vddvss Landed with https://reviews.llvm.org/rG884351547da27e76e14bef5fe20c3e3cb0e89acd, thanks for fixing it.
Dec 5 2019
Hi @vddvss do you need help landing this patch?
Dec 4 2019
clang-10: /home/buildslave/buildslave/clang-cmake-armv7-selfhost-neon/llvm/llvm/lib/CodeGen/MachineOperand.cpp:118: bool llvm::MachineOperand::isRenamable() const: Assertion `Register::isPhysicalRegister(getReg()) && "isRenamable should only be checked on physical registers"' failed.
It misses check if the register is zero before invoking isRenamable.
It breaks http://lab.llvm.org:8011/builders/clang-cmake-armv7-selfhost/builds/2747, reverted. I'll investigate it.
As a newbie of PowerPC backend, I think what @jsji proposed will ease my mind burden when faced with o ended instructions. I have read ISA-3.0 and know
A period (.) as the last character of an instruction mnemonic means that the instruction *records* sta- tus information in certain fields of the Condition Register as a side effect of execution.
I can directly react to the effect of record-form instruction if it ends with _record. If _record is too long, how about _rec, just like X86's _alt ended instructions?
Dec 3 2019
Dec 2 2019
Rebased and add comment for invalidateRegister.
LGTM. Thanks for fixing it. Personally, I would recommend Alive to verify peephole optimizations.
Nov 29 2019
The RISC-V test changes look good. (I do not intend to review the optimisation implementation or other backend test changes).
Rebased and fixed broken tests. Ready to be reviewed.
Nov 28 2019
Rebased and get broken tests, I'll investigate it and change this patch.
Nov 24 2019
What it broke seems to be tests on Power8.
Nov 20 2019
Nov 19 2019
LGTM considering patterns added for SIGN_EXTENDED_INREG also follow its atomic semantics.
I plan to move the two changed swap-le tests into another NFC patch, since they're not related to the logic.
I think all test cases change should be reflected so that reviewers can have a look if they are regressions.
Nov 18 2019
Add test case involving RegMask.
My concern is store and store volatile are so different in semantics that it might break original test intention.
Since d27a16eb392f39f9ee04ff5194b1eff3e189e6f8 reverts previous changes, LLVMDIBuilderCreateTypedef's signature becomes what it was. I'll revert this commit.