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Nov 12 2018

materi added a comment to D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor.

Some words about the different kinds of operands:

The extra operands do make sense semantically and are necessary for our modeling of things. The thing I regret though is that just being an implicit operand can mean two things today: It's an operand that isn't explicitly emitted to assembly/encoded or it's an operand that does not correspond to a read/write access in hardware or both. In this patch we only want to catch the 2nd kind, but not purely cases of the first. While it is unfortunate to not have this modeled as two separate bits today, it feels to me like the heuristic is close enough. Should we try again with an extra MO.isImplicit() in the condition?

I agree that this overloading is unfortunate! How hard would it be to split these operands in two different types?

Nov 12 2018, 7:19 AM

Nov 2 2018

materi added a comment to D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor.

I don't like any implementation that has first-class and second-class MachineOperands. At least I think it's a bad idea to have this in the default implementation, doing it in a target hook makes sense though.

I don't think having a target specific hook is good enough here because some of the problematic operands are generated by generic register allocation code; you will get them as soon as you have subregisters in the mix.

Nov 2 2018, 3:07 AM

Nov 1 2018

materi added a comment to D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor.

I'm wondering if we could maybe keep the old flexible way to look at MachineOperands and put the functionality which sets the latency to zero in the getOperandLatency hook instead?

@materi: I think your ideas make sense. If you have a patch, could you post it, please?

Nov 1 2018, 5:21 AM

Oct 31 2018

materi added a comment to D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor.

This patch is causing some problems in my out-of-tree back-end. We add some MachineOperands on the fly for some uses/defs that are conditional or depend on some circumstances, like how registers were allocated, or which depth a loop is at in a loop nest. With this patch, these manually added operands don't work as we intend.

Oct 31 2018, 6:05 AM

May 31 2018

materi added a watcher for debug-info: materi.
May 31 2018, 3:54 AM

May 24 2018

materi added inline comments to D46837: [MachineScheduler] Skip an implicit def of a super-reg added by regalloc in findDefIdx..
May 24 2018, 6:30 AM

Oct 20 2017

materi added a comment to D38101: [Sema] Diagnose tautological comparison with type's min/max values.

Hi!

Hi.

After this patch I started to see warnings:

Thank you for the report!

e.c:8:23: warning: integer constant not in range of enumerated type 'enum E' [-Wassign-enum]
  enum E {a = 7,} e = 1000;
                      ^
e.c:10:12: warning: comparison 'enum E' > 7 is always false [-Wtautological-constant-compare]
  return e > 7;

Isn't the the "always false" message misleading? It's only "always false" if e was initialized with an in-range value. Maybe the tautology check should be on the enum's underlying type instead?

I agree, please open a bug, i'll look into this.

Oct 20 2017, 12:38 AM · Restricted Project

Oct 19 2017

materi added a comment to D38101: [Sema] Diagnose tautological comparison with type's min/max values.

After this patch I started to see warnings:

Oct 19 2017, 10:02 AM · Restricted Project

Sep 12 2017

materi added inline comments to D35437: Don't break bundles when adding DBG_VALUE.
Sep 12 2017, 1:53 AM

May 29 2017

materi committed rL304149: Test commit: fix typos.
Test commit: fix typos
May 29 2017, 4:47 AM

May 22 2017

materi added a reviewer for D33408: MachineCSE: Respect interblock physreg liveness: qcolombet.
May 22 2017, 5:46 AM
materi created D33408: MachineCSE: Respect interblock physreg liveness.
May 22 2017, 5:42 AM

Feb 27 2017

materi added a comment to D29925: Implement intrinsic mangling for literal struct types. Fixes PR 31921.

Sorry about that.
I wasn't aware intrinsics were allowed to have a calling convention, since they are internal to llvm.
No intrinsic defined in Intrinsics* has one, from what i can tell, and as you can see, the code we use to upgrade generically does not do anything with calling convention either.
I'm not even sure what it would mean for an intrinsic to have a calling convention (instead of something it *lowers to* to have a calling convention).

Feb 27 2017, 3:55 AM
materi added a comment to D29925: Implement intrinsic mangling for literal struct types. Fixes PR 31921.

I think this commit is causing a bug in my out-of-tree target. From opt -lint I started seeing messages like this:

Feb 27 2017, 1:54 AM

May 16 2016

materi added a comment to D19630: Debug info: Support DWARF4 bitfields via DW_AT_data_bit_offset. .

Reported it here: https://llvm.org/bugs/show_bug.cgi?id=27758

May 16 2016, 9:28 AM
materi added a comment to D19630: Debug info: Support DWARF4 bitfields via DW_AT_data_bit_offset. .

I am debugging an issue with bitfields and debug info and found that this commit is where the problems begin.

May 16 2016, 9:06 AM

Feb 3 2016

materi added inline comments to D16829: An implementation of Swing Modulo Scheduling.
Feb 3 2016, 11:11 AM
materi added a comment to D16829: An implementation of Swing Modulo Scheduling.

This looks like a nice SMS implementation!

Feb 3 2016, 4:27 AM
materi updated subscribers of D16829: An implementation of Swing Modulo Scheduling.
Feb 3 2016, 3:39 AM

Oct 6 2015

materi updated subscribers of D13458: [SCEV] Pick backedge values for phi nodes correctly.
Oct 6 2015, 2:40 AM

Feb 24 2015

materi updated subscribers of D7850: ScheduleDAGInstrs::buildSchedGraph() rewritten..
Feb 24 2015, 5:14 AM