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Wed, May 5

evgeny777 accepted D101918: [clang][Driver] Add -fintegrate-as to debug-pass-structure test.

LGTM

Wed, May 5, 9:09 AM · Restricted Project

Tue, May 4

evgeny777 added a comment to D99599: [NewPM] Add an option to dump pass structure.

Could you explain why -debug-pass-manager doesn't fit your use case?

Tue, May 4, 9:33 AM · Restricted Project, Restricted Project

Mon, May 3

evgeny777 added a comment to D99599: [NewPM] Add an option to dump pass structure.

I've already run into having to update these two golden file tests twice

Mon, May 3, 11:42 PM · Restricted Project, Restricted Project

Fri, Apr 30

evgeny777 added a comment to D99599: [NewPM] Add an option to dump pass structure.

Should be fixed with c81ec19fba27ec

Fri, Apr 30, 12:19 AM · Restricted Project, Restricted Project
evgeny777 committed rGc81ec19fba27: Fix -fdebug-pass-structure test case (authored by evgeny777).
Fix -fdebug-pass-structure test case
Fri, Apr 30, 12:18 AM

Thu, Apr 29

evgeny777 added a comment to D99599: [NewPM] Add an option to dump pass structure.

Hm ... I see BarrierNoop pass being added before annotation-remarks. Why's that?

Thu, Apr 29, 10:52 AM · Restricted Project, Restricted Project
evgeny777 added a comment to D99599: [NewPM] Add an option to dump pass structure.

@haowei What are LLVM configuration options? Also please send output from

/opt/s/w/ir/x/w/staging/llvm_build/bin/clang -flegacy-pass-manager -fdebug-pass-structure -O0 -S -emit-llvm /opt/s/w/ir/x/w/llvm-project/clang/test/Driver/debug-pass-structure.c -o /dev/null 2>&1
Thu, Apr 29, 10:45 AM · Restricted Project, Restricted Project
evgeny777 committed rG6a0283d0d23c: [NewPM] Add an option to dump pass structure (authored by evgeny777).
[NewPM] Add an option to dump pass structure
Thu, Apr 29, 12:30 AM
evgeny777 closed D99599: [NewPM] Add an option to dump pass structure.
Thu, Apr 29, 12:29 AM · Restricted Project, Restricted Project

Wed, Apr 28

evgeny777 updated the diff for D99599: [NewPM] Add an option to dump pass structure.

Addressed comments

Wed, Apr 28, 8:24 AM · Restricted Project, Restricted Project
evgeny777 added inline comments to D99599: [NewPM] Add an option to dump pass structure.
Wed, Apr 28, 8:23 AM · Restricted Project, Restricted Project
evgeny777 updated the diff for D99599: [NewPM] Add an option to dump pass structure.

Added clang test

Wed, Apr 28, 4:09 AM · Restricted Project, Restricted Project
evgeny777 added inline comments to D99599: [NewPM] Add an option to dump pass structure.
Wed, Apr 28, 3:44 AM · Restricted Project, Restricted Project

Fri, Apr 23

evgeny777 updated the diff for D99599: [NewPM] Add an option to dump pass structure.

Addressed comments

Fri, Apr 23, 5:12 AM · Restricted Project, Restricted Project

Thu, Apr 15

evgeny777 requested review of D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).
Thu, Apr 15, 5:41 AM · Restricted Project
evgeny777 reopened D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).
Thu, Apr 15, 5:39 AM · Restricted Project
evgeny777 updated the diff for D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).

Rebased and addressed comments from @lattner (I've removed the dead-store-status.ll because it is specific to CleanupPointerRootUsers)

Thu, Apr 15, 5:39 AM · Restricted Project

Wed, Apr 14

evgeny777 added a comment to D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).

As far as I can tell, the breakage of -fsanitize=leak was not known prior to the commit

What kind of breakage? According to @MaskRay (I've just verified his code) LSAN detects memory leak when valgrind hack is reversed, so there is at least some improvement, not breakage. Even if LSAN needs to keep pointer globals for some reason then it can do so from instrumentation pass, because LSAN is part of LLVM. I see no reason why hacks should reside in LLVM trunk to appease some third party tools.

Wed, Apr 14, 8:13 AM · Restricted Project
evgeny777 added a comment to D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).

Just how much do we gain by eliminating these locations? Are we talking 10%, 1%, or what?

I don't know, but preventing optimization to appease valgrind looks .. hm.. strange. I agree with @nlopes that __attribute__((__used__)) should be used for such purpose (probably added from some instrumentation pass)

Wed, Apr 14, 3:23 AM · Restricted Project

Tue, Apr 13

evgeny777 committed rGf1a4df542dfb: Remove empty test case (authored by evgeny777).
Remove empty test case
Tue, Apr 13, 9:17 AM
evgeny777 committed rGdbc16ed199dc: [GlobalOpt] Revert valgrind hacks (authored by evgeny777).
[GlobalOpt] Revert valgrind hacks
Tue, Apr 13, 9:11 AM
evgeny777 closed D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).
Tue, Apr 13, 9:11 AM · Restricted Project

Apr 1 2021

evgeny777 updated the diff for D99599: [NewPM] Add an option to dump pass structure.

Fix windows buildbot failure

Apr 1 2021, 1:16 AM · Restricted Project, Restricted Project

Mar 30 2021

evgeny777 added inline comments to D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).
Mar 30 2021, 9:06 AM · Restricted Project
evgeny777 requested review of D99599: [NewPM] Add an option to dump pass structure.
Mar 30 2021, 8:42 AM · Restricted Project, Restricted Project
evgeny777 added a comment to D69428: [GlobalOpt] Remove valgrind specific hacks (revert r160529).

@nlopes

Not sure you are still interested in this patch. If so, I would suggest you get in touch with some Google folks and check with them if their codebase is ready for this patch. They were the only reason for this workaround.

Mar 30 2021, 2:51 AM · Restricted Project

Dec 30 2020

evgeny777 added a comment to D92296: [AARCH64] Improve accumulator forwarding for Cortex-A57 model.

Regarding the PMUL latency the optimization guide says this. AArch64SchedA57.td probably has older latencies. Should these be updated?

Dec 30 2020, 9:48 AM · Restricted Project

Dec 21 2020

evgeny777 added inline comments to D92296: [AARCH64] Improve accumulator forwarding for Cortex-A57 model.
Dec 21 2020, 4:35 AM · Restricted Project

Dec 7 2020

evgeny777 committed rG53401e8e8864: [TableGen][SchedModels] Simplify the code. NFC (authored by evgeny777).
[TableGen][SchedModels] Simplify the code. NFC
Dec 7 2020, 12:54 AM
evgeny777 closed D92304: [TableGen][SchedModels] Simplify the code. NFC.
Dec 7 2020, 12:53 AM · Restricted Project

Dec 4 2020

evgeny777 committed rGf69936f52973: Attempt to fix buildbot after rG993eaf2d69d8 (authored by evgeny777).
Attempt to fix buildbot after rG993eaf2d69d8
Dec 4 2020, 11:10 AM
evgeny777 added a comment to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

Recommitted in rG993eaf2d69d8

Dec 4 2020, 10:52 AM · Restricted Project
evgeny777 committed rG993eaf2d69d8: Recommit [TableGen][SchedModels] Fix read/write variant substitution (authored by evgeny777).
Recommit [TableGen][SchedModels] Fix read/write variant substitution
Dec 4 2020, 10:50 AM
evgeny777 accepted D92599: Fix for Bug 48055..

LGTM

Dec 4 2020, 9:48 AM · Restricted Project
evgeny777 added a comment to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

^ Oh that's a shame. Any idea what was causing the output to be different? This fixed a problem we were seeing (and are now seeing again) in one of our downstream schedules.

Dec 4 2020, 8:44 AM · Restricted Project

Nov 30 2020

evgeny777 updated the diff for D92304: [TableGen][SchedModels] Simplify the code. NFC.

Also simplify CodeGenSchedTransition

Nov 30 2020, 3:25 AM · Restricted Project
evgeny777 requested review of D92304: [TableGen][SchedModels] Simplify the code. NFC.
Nov 30 2020, 2:41 AM · Restricted Project
evgeny777 committed rG129523588f27: Fix test case (authored by evgeny777).
Fix test case
Nov 30 2020, 1:35 AM
evgeny777 committed rG112b3cb6ba49: [TableGen][SchedModels] Fix read/write variant substitution (authored by evgeny777).
[TableGen][SchedModels] Fix read/write variant substitution
Nov 30 2020, 12:56 AM
evgeny777 closed D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.
Nov 30 2020, 12:56 AM · Restricted Project

Nov 27 2020

evgeny777 added a comment to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

Patch also lowers time of AArch64 subtarget generation from ~13s to ~10s in Debug build and from ~6s to 2.5s in Release build on my PC

Nov 27 2020, 9:36 AM · Restricted Project
evgeny777 updated the diff for D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

@dmgreen After some studying I came up with different approach: if we get rid of artifical 'AnyCPU' (zero) processor index and explicitly create one PredTransition per processor, we can use much simpler algorithm for variant expansion. Besides fixing read variant compilation issues this also fixes few other things:

Nov 27 2020, 9:00 AM · Restricted Project
evgeny777 committed rG4c419c454ad2: [TableGen][SchedModels] Get rid of hasVariant. NFC (authored by evgeny777).
[TableGen][SchedModels] Get rid of hasVariant. NFC
Nov 27 2020, 7:00 AM
evgeny777 closed D92026: [TableGen][SchedModels] Get rid of hasVariant. NFC.
Nov 27 2020, 7:00 AM · Restricted Project

Nov 25 2020

evgeny777 committed rGd8f22c77699f: [SchedModels] Return earlier removed checks (authored by evgeny777).
[SchedModels] Return earlier removed checks
Nov 25 2020, 1:07 AM

Nov 24 2020

evgeny777 added a comment to D92026: [TableGen][SchedModels] Get rid of hasVariant. NFC.

@andreadb Built all targets, looks like none is touched (checked RISCV, AMDGPU, PPC, Lanai, etc)

Nov 24 2020, 11:54 PM · Restricted Project
evgeny777 added a comment to D92026: [TableGen][SchedModels] Get rid of hasVariant. NFC.

When you say that " Subtarget files are unchanged by the patch", does it mean that you have checked all the targets or just ARM?

Nov 24 2020, 7:53 AM · Restricted Project
evgeny777 committed rG9c3b68dc6fe1: [llvm-mca] Fix processing thumb instruction set (authored by evgeny777).
[llvm-mca] Fix processing thumb instruction set
Nov 24 2020, 7:28 AM
evgeny777 closed D91704: [llvm-mca] Fix processing thumb instruction set.
Nov 24 2020, 7:28 AM · Restricted Project
evgeny777 planned changes to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

Needs to be rebased

Nov 24 2020, 7:13 AM · Restricted Project
evgeny777 committed rGa6a6d11c7b05: [MC][ARM] Fix number of operands of tMOVSr (authored by evgeny777).
[MC][ARM] Fix number of operands of tMOVSr
Nov 24 2020, 7:13 AM
evgeny777 closed D92029: [MC][ARM] Fix number of operands of tMOVSr.
Nov 24 2020, 7:13 AM · Restricted Project
evgeny777 updated the diff for D91704: [llvm-mca] Fix processing thumb instruction set.

Addressed. Revision now depends on D92029

Nov 24 2020, 7:05 AM · Restricted Project
evgeny777 requested review of D92029: [MC][ARM] Fix number of operands of tMOVSr.
Nov 24 2020, 6:50 AM · Restricted Project
evgeny777 requested review of D92026: [TableGen][SchedModels] Get rid of hasVariant. NFC.
Nov 24 2020, 6:29 AM · Restricted Project
evgeny777 committed rGa2b59048d990: [SchedModels] Improve diagnostics. NFC (authored by evgeny777).
[SchedModels] Improve diagnostics. NFC
Nov 24 2020, 2:53 AM
evgeny777 committed rG78caf4f1bb13: [SchedModels] Limit set of predicates seen by mutuallyExclusive (authored by evgeny777).
[SchedModels] Limit set of predicates seen by mutuallyExclusive
Nov 24 2020, 1:44 AM
evgeny777 committed rG50bd686695ac: Add support for branch forms of ALU instructions to Cortex-A57 model (authored by evgeny777).
Add support for branch forms of ALU instructions to Cortex-A57 model
Nov 24 2020, 12:44 AM
evgeny777 closed D91266: [ARM][SchedModels] Add support for branch forms of ALU instructions to Cortex-A57 model.
Nov 24 2020, 12:44 AM · Restricted Project

Nov 23 2020

evgeny777 updated the diff for D91704: [llvm-mca] Fix processing thumb instruction set.

Addressed. Thanks for insights!

Nov 23 2020, 11:51 PM · Restricted Project
evgeny777 accepted D91812: [ThinLTO/WPD] Enable -wholeprogramdevirt-skip in ThinLTO backends.

Thanks, LGTM

Nov 23 2020, 10:20 PM · Restricted Project, Restricted Project
evgeny777 updated the diff for D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

@dmgreen Nice find again, thanks. Somehow I missed that. I've fixed the issue and checked ARM and AArch64 targets - looks good so far.

Nov 23 2020, 10:02 AM · Restricted Project
evgeny777 added inline comments to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.
Nov 23 2020, 9:49 AM · Restricted Project
evgeny777 added inline comments to D91704: [llvm-mca] Fix processing thumb instruction set.
Nov 23 2020, 3:36 AM · Restricted Project
evgeny777 updated the diff for D91266: [ARM][SchedModels] Add support for branch forms of ALU instructions to Cortex-A57 model.

Addressed

Nov 23 2020, 1:56 AM · Restricted Project
evgeny777 updated the diff for D91704: [llvm-mca] Fix processing thumb instruction set.
  • Added check for Thumb1, because Thumb2 instructions follow different encoding rules
  • Added comments
Nov 23 2020, 1:27 AM · Restricted Project
evgeny777 added inline comments to D91704: [llvm-mca] Fix processing thumb instruction set.
Nov 23 2020, 1:13 AM · Restricted Project

Nov 18 2020

evgeny777 requested review of D91704: [llvm-mca] Fix processing thumb instruction set.
Nov 18 2020, 6:08 AM · Restricted Project

Nov 11 2020

evgeny777 updated the diff for D91266: [ARM][SchedModels] Add support for branch forms of ALU instructions to Cortex-A57 model.

Fixed issue with accessing wrong element in vector

Nov 11 2020, 9:01 AM · Restricted Project
evgeny777 updated the summary of D91266: [ARM][SchedModels] Add support for branch forms of ALU instructions to Cortex-A57 model.
Nov 11 2020, 7:53 AM · Restricted Project
evgeny777 requested review of D91266: [ARM][SchedModels] Add support for branch forms of ALU instructions to Cortex-A57 model.
Nov 11 2020, 7:47 AM · Restricted Project

Nov 9 2020

evgeny777 committed rG885d3f412946: [llvm-mca] Add branch forms of ALU instructions to Cortex-A57 test (authored by evgeny777).
[llvm-mca] Add branch forms of ALU instructions to Cortex-A57 test
Nov 9 2020, 5:54 AM
evgeny777 added inline comments to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.
Nov 9 2020, 4:25 AM · Restricted Project

Nov 7 2020

evgeny777 added inline comments to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.
Nov 7 2020, 10:38 AM · Restricted Project
evgeny777 added a comment to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

I'm not sure if I see how both halves are related here. Is this a problem that you found, so you altered the A57 to show that issue, so the tablegen code fixes the issue?

Nov 7 2020, 10:32 AM · Restricted Project

Nov 6 2020

evgeny777 updated the diff for D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

Eliminated unused variable

Nov 6 2020, 12:50 AM · Restricted Project

Nov 5 2020

evgeny777 updated the diff for D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

Simplified

Nov 5 2020, 7:40 AM · Restricted Project
evgeny777 requested review of D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.
Nov 5 2020, 5:55 AM · Restricted Project

Nov 2 2020

evgeny777 committed rGcc96a822917c: [TableGen][SchedModels] Fix read/write variant substitution (authored by evgeny777).
[TableGen][SchedModels] Fix read/write variant substitution
Nov 2 2020, 6:39 AM
evgeny777 closed D89777: [TableGen][SchedModels] Fix read/write variant substitution.
Nov 2 2020, 6:39 AM · Restricted Project

Oct 30 2020

evgeny777 updated the diff for D89777: [TableGen][SchedModels] Fix read/write variant substitution.

@dmgreen Nice find! I've fixed it

Oct 30 2020, 11:52 AM · Restricted Project

Oct 29 2020

evgeny777 updated the diff for D89777: [TableGen][SchedModels] Fix read/write variant substitution.

Addressed

Oct 29 2020, 1:59 AM · Restricted Project
evgeny777 added a comment to D89777: [TableGen][SchedModels] Fix read/write variant substitution.

Ping

Oct 29 2020, 1:18 AM · Restricted Project

Oct 26 2020

evgeny777 committed rGa28388f95beb: [ARM][SchedModels] Move IsLDMBaseRegInListPred to ARMSchedule.td. NFC (authored by evgeny777).
[ARM][SchedModels] Move IsLDMBaseRegInListPred to ARMSchedule.td. NFC
Oct 26 2020, 12:32 PM
evgeny777 committed rGe74f66125ebb: [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate
Oct 26 2020, 10:23 AM
evgeny777 closed D90150: [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate.
Oct 26 2020, 10:23 AM · Restricted Project
evgeny777 committed rGa877bda397bb: Fix issue in cortex-a57 sched model (authored by evgeny777).
Fix issue in cortex-a57 sched model
Oct 26 2020, 10:17 AM
evgeny777 closed D90152: Fix issue in cortex-a57 sched model.
Oct 26 2020, 10:17 AM · Restricted Project
evgeny777 updated the diff for D90150: [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate.

Addressed

Oct 26 2020, 7:40 AM · Restricted Project
evgeny777 requested review of D90152: Fix issue in cortex-a57 sched model.
Oct 26 2020, 5:24 AM · Restricted Project
evgeny777 requested review of D90150: [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate.
Oct 26 2020, 5:02 AM · Restricted Project
evgeny777 committed rG1876d06ea31f: [llvm-mca] Add few memory instructions to cortex-a57 test (authored by evgeny777).
[llvm-mca] Add few memory instructions to cortex-a57 test
Oct 26 2020, 4:19 AM
evgeny777 committed rGa95ce5f65f13: [ARM][SchedModels] Rename and generalize predicate. NFC (authored by evgeny777).
[ARM][SchedModels] Rename and generalize predicate. NFC
Oct 26 2020, 2:15 AM
evgeny777 committed rG99b2756517f2: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred (authored by evgeny777).
[ARM][SchedModels] Get rid of IsLdrAm2ScaledPred
Oct 26 2020, 2:02 AM
evgeny777 closed D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .
Oct 26 2020, 2:02 AM · Restricted Project
evgeny777 committed rGa4fc18e6410f: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate
Oct 26 2020, 1:55 AM
evgeny777 closed D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate.
Oct 26 2020, 1:54 AM · Restricted Project
evgeny777 committed rGd613e39d52d2: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate (authored by evgeny777).
[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate
Oct 26 2020, 1:43 AM
evgeny777 closed D90045: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate.
Oct 26 2020, 1:43 AM · Restricted Project

Oct 23 2020

evgeny777 added a comment to D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred .

(paranoia level).
Are we sure that the lowering of MachineInstr to MCInst is preserving the operand sequence? Can it be that the immediate is at position 4 for the MCInst only?
I have no idea how an ldrbt looks like as a MachineInstr. The original check should have triggered an assertion too for MachineInstr then...

Oct 23 2020, 9:52 AM · Restricted Project