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Tue, Aug 20

hliao committed rGa99086dbdd92: [Attributor] Remove unused variable. NFC. (authored by hliao).
[Attributor] Remove unused variable. NFC.
Tue, Aug 20, 2:04 PM
hliao committed rL369444: [Attributor] Remove unused variable. NFC..
[Attributor] Remove unused variable. NFC.
Tue, Aug 20, 2:04 PM

Wed, Aug 14

hliao accepted D66170: InferAddressSpaces: Move target intrinsic handling to TTI.

LGTM

Wed, Aug 14, 9:32 AM
hliao added inline comments to D66170: InferAddressSpaces: Move target intrinsic handling to TTI.
Wed, Aug 14, 8:05 AM
hliao added inline comments to D66170: InferAddressSpaces: Move target intrinsic handling to TTI.
Wed, Aug 14, 6:37 AM

Tue, Aug 13

hliao committed rG44e6c6bd2f05: Remove the extra `;`. (authored by hliao).
Remove the extra `;`.
Tue, Aug 13, 2:30 PM
hliao committed rL368748: Remove the extra `;`..
Remove the extra `;`.
Tue, Aug 13, 2:26 PM

Sat, Aug 10

hliao committed rG8a25eabd4278: [TableGen] Correct the shift to the proper bit width. (authored by hliao).
[TableGen] Correct the shift to the proper bit width.
Sat, Aug 10, 9:15 AM
hliao committed rL368513: [TableGen] Correct the shift to the proper bit width..
[TableGen] Correct the shift to the proper bit width.
Sat, Aug 10, 9:15 AM

Tue, Jul 30

hliao abandoned D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..
Tue, Jul 30, 3:56 PM · Restricted Project
hliao committed rGf3983cc14af3: [NVPTX] Fix PR41651 (authored by hliao).
[NVPTX] Fix PR41651
Tue, Jul 30, 12:53 PM
hliao committed rL367349: [NVPTX] Fix PR41651.
[NVPTX] Fix PR41651
Tue, Jul 30, 12:53 PM
hliao closed D65468: [NVPTX] Fix PR41651.
Tue, Jul 30, 12:53 PM · Restricted Project
hliao updated the diff for D65468: [NVPTX] Fix PR41651.

simplify the patch

Tue, Jul 30, 12:47 PM · Restricted Project
hliao added inline comments to D65468: [NVPTX] Fix PR41651.
Tue, Jul 30, 12:47 PM · Restricted Project
hliao added inline comments to D65468: [NVPTX] Fix PR41651.
Tue, Jul 30, 12:39 PM · Restricted Project
hliao added reviewers for D65468: [NVPTX] Fix PR41651: jholewinski, timshen.
Tue, Jul 30, 12:15 PM · Restricted Project
hliao created D65468: [NVPTX] Fix PR41651.
Tue, Jul 30, 12:12 PM · Restricted Project
hliao committed rG0d6615cc1911: [Support] Workaround a GCC 4.8 bug on constant expression evaluation. (authored by hliao).
[Support] Workaround a GCC 4.8 bug on constant expression evaluation.
Tue, Jul 30, 9:12 AM
hliao committed rL367329: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..
[Support] Workaround a GCC 4.8 bug on constant expression evaluation.
Tue, Jul 30, 9:11 AM
hliao closed D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..
Tue, Jul 30, 9:11 AM · Restricted Project
hliao added a comment to D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..

But one can use devtoolset on centos/rhel :)

There is a llvm-dev discusion (but now dead, Google blocked it? @jfb @chandlerc) about bumping gcc versions, LLVM wants to use C++-14.

Anyway, this small change looks fine.

Tue, Jul 30, 9:10 AM · Restricted Project
hliao added a comment to D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..

Is it worth to workaround old gcc?

Support for gcc 4.8 will be dropped soon(ish) anyway..

Tue, Jul 30, 9:00 AM · Restricted Project
hliao added a comment to D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..

BTW, if I read that correct, even though gcc 5.1 is listed as requirement, but that page also mentioned that gcc 4.8 could compile correctly the current LLVM codebase, https://llvm.org/docs/GettingStarted.html#host-c-toolchain-both-compiler-and-standard-library. As gcc 4.8.x is widely used in many long-term maintained systems, it would be nice to compile LLVM correctly against it.

Tue, Jul 30, 8:06 AM · Restricted Project
hliao added a comment to D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..

https://llvm.org/docs/GettingStarted.html#id7

GCC >=5.1.0 C/C++ compiler

The current recommendation is >=5.1.0...

Tue, Jul 30, 8:00 AM · Restricted Project
hliao updated the diff for D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..

Format the commit message

Tue, Jul 30, 7:59 AM · Restricted Project
hliao updated the summary of D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..
Tue, Jul 30, 7:57 AM · Restricted Project
hliao created D65452: [Support] Workaround a GCC 4.8 bug on constant expression evaluation..
Tue, Jul 30, 7:50 AM · Restricted Project

Fri, Jul 26

hliao committed rG711556e6a828: [AMDGPU] Fix typo. (authored by hliao).
[AMDGPU] Fix typo.
Fri, Jul 26, 10:14 AM
hliao committed rL367131: [AMDGPU] Fix typo..
[AMDGPU] Fix typo.
Fri, Jul 26, 10:13 AM

Thu, Jul 25

hliao committed rG53f967f2bdb6: [AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs. (authored by hliao).
[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs.
Thu, Jul 25, 7:52 AM
hliao committed rL367023: [AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs..
[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs.
Thu, Jul 25, 7:50 AM
hliao closed D64353: [AMDGPU] Run '' after isel to simplify PHIs..
Thu, Jul 25, 7:50 AM · Restricted Project
hliao abandoned D64144: [AMDGPU] Update NumUserSGPRs and NumSystemSGPRs in MIR parsing..
Thu, Jul 25, 6:36 AM · Restricted Project

Jul 24 2019

hliao updated the diff for D64353: [AMDGPU] Run '' after isel to simplify PHIs..

Add fixme.

Jul 24 2019, 7:16 PM · Restricted Project

Jul 22 2019

hliao added a comment to D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..

when we insert that copy, if we still follow the current logic of phi-elim, that COPY is already inserted after its use (that CF_END).

Jul 22 2019, 6:02 AM · Restricted Project

Jul 19 2019

hliao added a comment to D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..

It sounds to me that additional hook is a clear change. Or, we need to change the existing hook from const MachineInstr & to MachineInstr & to allow changing instruction. Any idea?

Jul 19 2019, 11:56 AM · Restricted Project
hliao committed rGff9c9e644db9: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass (authored by hliao).
[AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass
Jul 19 2019, 11:52 AM
hliao committed rL366602: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass.
[AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass
Jul 19 2019, 11:51 AM
hliao closed D64273: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass.
Jul 19 2019, 11:51 AM · Restricted Project

Jul 18 2019

hliao added inline comments to D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..
Jul 18 2019, 1:49 PM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

Please review https://reviews.llvm.org/D64946 following your suggestion.

Jul 18 2019, 1:32 PM · Restricted Project
hliao created D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..
Jul 18 2019, 1:32 PM · Restricted Project
hliao committed rG17a8a9277c11: [LAA] Re-check bit-width of pointers after stripping. (authored by hliao).
[LAA] Re-check bit-width of pointers after stripping.
Jul 18 2019, 10:33 AM
hliao committed rL366470: [LAA] Re-check bit-width of pointers after stripping..
[LAA] Re-check bit-width of pointers after stripping.
Jul 18 2019, 10:32 AM
hliao closed D64928: [LAA] Re-check bit-width of pointers after stripping..
Jul 18 2019, 10:32 AM · Restricted Project
hliao committed rG9ad917c2da72: Minor styling fix. NFC. (authored by hliao).
Minor styling fix. NFC.
Jul 18 2019, 9:15 AM
hliao committed rL366456: Minor styling fix. NFC..
Minor styling fix. NFC.
Jul 18 2019, 9:14 AM
hliao added a comment to D64928: [LAA] Re-check bit-width of pointers after stripping..

a similar case to https://reviews.llvm.org/D64768

Jul 18 2019, 9:06 AM · Restricted Project
hliao created D64928: [LAA] Re-check bit-width of pointers after stripping..
Jul 18 2019, 9:06 AM · Restricted Project

Jul 17 2019

hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

No matter what, running UnreachableMachineBlockElim is not a fix for this.

I think you should probably fix SILowerControlFlow

the misplacement of def/use is not the fault of SILowerControlFlow but PHIEliminate. However, even PHIEliminate should not be blamed as cf.end is part of MBB prologue. cf.end should not take any input from PHI.

In O2 compilation, there won't be such issue as, in optimized RA, livevariable is used to eliminate PHI better. LiveVariables depends on unreachable-mbb-elimin, which remove the PHI to cf.end.

This isn't a property the pass should rely on. SILowerControlFlow should defend against unexpected iteration order and unreachable blocks

any use before def is invalid MIR, right?

So the MIR is valid before phi elimination, and then becomes invalid after. Removing unreachable blocks earlier to avoid this happening is a workaround. It seems to me like we need to fix PHI elimination or avoid relying on the prolog instructions

my understanding is that MBB prologue instructions are designed NOT to take PHI as input. Like these pseudo instructions for structurized CFG, by design, they don't take any PHI as input. As an alternative approach (not workaround), we could ensure these instructions not taking PHI as input before PHIElim instead of teaching PHIElim to under them, more or less very target-specific stuff.

The verifier should probably check this. We definitely should not hack around this by deleting unreachable blocks that happens to run into this

Jul 17 2019, 12:27 PM · Restricted Project

Jul 16 2019

hliao committed rGccf22ef94c4a: Fix -Wreturn-type warning. NFC. (authored by hliao).
Fix -Wreturn-type warning. NFC.
Jul 16 2019, 1:00 PM
hliao committed rL366251: Fix -Wreturn-type warning. NFC..
Fix -Wreturn-type warning. NFC.
Jul 16 2019, 1:00 PM
hliao committed rGb3f967d41135: [AMDGPU] Add the adjusted FP as a livein register. (authored by hliao).
[AMDGPU] Add the adjusted FP as a livein register.
Jul 16 2019, 9:00 AM
hliao committed rL366223: [AMDGPU] Add the adjusted FP as a livein register..
[AMDGPU] Add the adjusted FP as a livein register.
Jul 16 2019, 8:59 AM
hliao closed D64145: [AMDGPU] Add the adjusted FP as a livein register..
Jul 16 2019, 8:59 AM · Restricted Project
hliao added a comment to D64145: [AMDGPU] Add the adjusted FP as a livein register..

LGTM with nit

Jul 16 2019, 8:58 AM · Restricted Project
hliao updated the diff for D64145: [AMDGPU] Add the adjusted FP as a livein register..

revise the test case

Jul 16 2019, 6:50 AM · Restricted Project

Jul 15 2019

hliao committed rG543ba4e9e0c4: [InstructionSimplify] Apply sext/trunc after pointer stripping (authored by hliao).
[InstructionSimplify] Apply sext/trunc after pointer stripping
Jul 15 2019, 6:04 PM
hliao committed rL366162: [InstructionSimplify] Apply sext/trunc after pointer stripping.
[InstructionSimplify] Apply sext/trunc after pointer stripping
Jul 15 2019, 6:03 PM
hliao closed D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.
Jul 15 2019, 6:03 PM · Restricted Project
hliao added a comment to D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.

LGTM, one request and a proposal to fix it slightly differently.

This is fine with me. Though, I'm unsure if this should not live in the stripAndAccumulateConstantOffsets method.

The problem is that we have two bit-widths now, pointer before and after. Since we have to express offset in one of them, we have a choice.
I think we already guarantee that the offset is representable in the initial bit-width so that was what I choose. Question is, do we want
to change it to be in the resulting bit-width or not. Either way, we should add a comment to the stripAndAccumulateConstantOffsets method
explaining the situation.

As I mentioned, without this fix, there are crashes when compiling similar patterns. The issue is that LHS gets the original bit-width as the offset is 0 and RHS gets the one after stripping. Later, as the stripped pointers point the same object, instsimplify will create compare of the offset, that triggers the crash. We have to ensure offset after stripping has the same bit-width.

I understand. That is what I tried to describe above. My question was: Should stripAndAccumulateConstantOffsets return the offset wrt. the bit-width of the input pointer or output pointer? I can see arguments for both. If you think this way is better you can go ahead and commit. If you think the other way around is better, we should move the conversion into stripAndAccumulateConstantOffsets. I personally tend towards the latter.

Either way, we have to add a comment to the stripAndAccumulateConstantOffsets method explaining the choice!

Jul 15 2019, 6:02 PM · Restricted Project
hliao added a comment to D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.

This is fine with me. Though, I'm unsure if this should not live in the stripAndAccumulateConstantOffsets method.

The problem is that we have two bit-widths now, pointer before and after. Since we have to express offset in one of them, we have a choice.
I think we already guarantee that the offset is representable in the initial bit-width so that was what I choose. Question is, do we want
to change it to be in the resulting bit-width or not. Either way, we should add a comment to the stripAndAccumulateConstantOffsets method
explaining the situation.

Jul 15 2019, 3:16 PM · Restricted Project
hliao added a comment to D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.

this fixes crashes found on targets where addrspacecast is used.

Jul 15 2019, 1:48 PM · Restricted Project
hliao created D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.
Jul 15 2019, 1:48 PM · Restricted Project

Jul 13 2019

hliao committed rG124cae7d3fc5: Remove extra ';' to silent compiler warning. (authored by hliao).
Remove extra ';' to silent compiler warning.
Jul 13 2019, 12:53 PM
hliao committed rL366010: Remove extra ';' to silent compiler warning..
Remove extra ';' to silent compiler warning.
Jul 13 2019, 12:49 PM

Jul 11 2019

hliao committed rG16d3c1ac03d3: [AMDGPU] Skip calculating callee saved registers for entry function. (authored by hliao).
[AMDGPU] Skip calculating callee saved registers for entry function.
Jul 11 2019, 4:54 PM
hliao committed rL365846: [AMDGPU] Skip calculating callee saved registers for entry function..
[AMDGPU] Skip calculating callee saved registers for entry function.
Jul 11 2019, 4:53 PM
hliao closed D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Jul 11 2019, 4:53 PM · Restricted Project
hliao added a comment to D64596: [AMDGPU] Skip calculating callee saved registers for entry function..

What is this supposed to solve?

Jul 11 2019, 2:26 PM · Restricted Project
hliao updated the diff for D64596: [AMDGPU] Skip calculating callee saved registers for entry function..

skip determining callee saved scalar register as well.

Jul 11 2019, 2:22 PM · Restricted Project
hliao added inline comments to D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Jul 11 2019, 2:17 PM · Restricted Project
hliao added inline comments to D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Jul 11 2019, 2:16 PM · Restricted Project
hliao created D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Jul 11 2019, 2:10 PM · Restricted Project
hliao added a comment to D64557: Add llvm.loop.licm.disable metadata.

please update the doc on transformation metadata

Jul 11 2019, 5:58 AM · Restricted Project

Jul 10 2019

hliao accepted D64478: AMDGPU: Serialize mode from MachineFunctionInfo.

LGTM

Jul 10 2019, 7:35 AM

Jul 9 2019

hliao committed rG9cf71d10f826: [unittest] Add the missing bogus machine register info initialization. (authored by hliao).
[unittest] Add the missing bogus machine register info initialization.
Jul 9 2019, 11:24 AM
hliao committed rL365529: [unittest] Add the missing bogus machine register info initialization..
[unittest] Add the missing bogus machine register info initialization.
Jul 9 2019, 11:22 AM
hliao committed rG329c03204069: [unittest] Add bogus register info. (authored by hliao).
[unittest] Add bogus register info.
Jul 9 2019, 10:20 AM
hliao committed rL365516: [unittest] Add bogus register info..
[unittest] Add bogus register info.
Jul 9 2019, 10:18 AM
hliao closed D64421: [unittest] Add bogus register info..
Jul 9 2019, 10:18 AM · Restricted Project
hliao added a comment to D64421: [unittest] Add bogus register info..

LGTM, although these should probably be the default implementations anyway

Jul 9 2019, 10:18 AM · Restricted Project
hliao updated the summary of D64421: [unittest] Add bogus register info..
Jul 9 2019, 9:03 AM · Restricted Project
hliao created D64421: [unittest] Add bogus register info..
Jul 9 2019, 8:20 AM · Restricted Project

Jul 8 2019

hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I think you should probably fix SILowerControlFlow

the misplacement of def/use is not the fault of SILowerControlFlow but PHIEliminate. However, even PHIEliminate should not be blamed as cf.end is part of MBB prologue. cf.end should not take any input from PHI.

In O2 compilation, there won't be such issue as, in optimized RA, livevariable is used to eliminate PHI better. LiveVariables depends on unreachable-mbb-elimin, which remove the PHI to cf.end.

This isn't a property the pass should rely on. SILowerControlFlow should defend against unexpected iteration order and unreachable blocks

any use before def is invalid MIR, right?

So the MIR is valid before phi elimination, and then becomes invalid after. Removing unreachable blocks earlier to avoid this happening is a workaround. It seems to me like we need to fix PHI elimination or avoid relying on the prolog instructions

Jul 8 2019, 11:53 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

cf.end and related MBB prologue instructions should not take PHIs as input. Before LCSSA is turned on, we won't have that IR. After LCSSA, the only possible PHI input is the one from non-latch loop single exit. That PHI is unnecessary and should be removed early to assure that the later passes could relies on the fact they cf.end and etc. won't take PHI as input.

Jul 8 2019, 11:20 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I think you should probably fix SILowerControlFlow

the misplacement of def/use is not the fault of SILowerControlFlow but PHIEliminate. However, even PHIEliminate should not be blamed as cf.end is part of MBB prologue. cf.end should not take any input from PHI.

In O2 compilation, there won't be such issue as, in optimized RA, livevariable is used to eliminate PHI better. LiveVariables depends on unreachable-mbb-elimin, which remove the PHI to cf.end.

This isn't a property the pass should rely on. SILowerControlFlow should defend against unexpected iteration order and unreachable blocks

Jul 8 2019, 11:11 AM · Restricted Project
hliao updated the diff for D64353: [AMDGPU] Run '' after isel to simplify PHIs..

revise test case

Jul 8 2019, 11:11 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I think you should probably fix SILowerControlFlow

Jul 8 2019, 11:05 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I'm still confused. When I try your testcase, I see an earlier iterator crash in SILowerControlFlow

Jul 8 2019, 10:11 AM · Restricted Project
hliao added inline comments to D64353: [AMDGPU] Run '' after isel to simplify PHIs..
Jul 8 2019, 9:58 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I don't follow how eliminating unreachable blocks fixes this.

In general expecting code placement with the block "prolog" instructions isn't reliable. I had fixed this in rL357634, except it was reverted

Jul 8 2019, 9:56 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I don't follow how eliminating unreachable blocks fixes this.

In general expecting code placement with the block "prolog" instructions isn't reliable. I had fixed this in rL357634, except it was reverted

Jul 8 2019, 9:56 AM · Restricted Project
hliao updated the diff for D64353: [AMDGPU] Run '' after isel to simplify PHIs..

revise commit message.

Jul 8 2019, 9:50 AM · Restricted Project
hliao created D64353: [AMDGPU] Run '' after isel to simplify PHIs..
Jul 8 2019, 9:44 AM · Restricted Project

Jul 6 2019

hliao updated the diff for D64273: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass.

revise the test function name

Jul 6 2019, 4:24 AM · Restricted Project

Jul 5 2019

hliao committed rG88b0d20edf67: Revert "[FileCheck] Simplify numeric variable interface" (authored by hliao).
Revert "[FileCheck] Simplify numeric variable interface"
Jul 5 2019, 3:28 PM
hliao added a reverting change for rG096600a4b073: [FileCheck] Simplify numeric variable interface: rG88b0d20edf67: Revert "[FileCheck] Simplify numeric variable interface".
Jul 5 2019, 3:27 PM
hliao committed rL365251: Revert "[FileCheck] Simplify numeric variable interface".
Revert "[FileCheck] Simplify numeric variable interface"
Jul 5 2019, 3:23 PM