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HsiangKai updated the diff for D100658: [RISCV] Apply __clang_riscv_builtin_alias to overloaded builtins..

Consider PermuteOperands.

Sat, Apr 17, 6:34 PM · Restricted Project

Fri, Apr 16

HsiangKai added inline comments to D100574: [RISCV][WIP] Fix missing emergency slots for scalable stack offsets.
Fri, Apr 16, 7:46 PM · Restricted Project
HsiangKai added a comment to D100574: [RISCV][WIP] Fix missing emergency slots for scalable stack offsets.

Thanks for the help. Do you want to create your own patch, or shall I incorporate your patch to reduce the number of registers into this (with attribution)?

Fri, Apr 16, 7:39 PM · Restricted Project
HsiangKai updated the summary of D100658: [RISCV] Apply __clang_riscv_builtin_alias to overloaded builtins..
Fri, Apr 16, 9:11 AM · Restricted Project
HsiangKai requested review of D100658: [RISCV] Apply __clang_riscv_builtin_alias to overloaded builtins..
Fri, Apr 16, 9:08 AM · Restricted Project
HsiangKai updated the diff for D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics..

Add a negative test case.

Fri, Apr 16, 7:26 AM · Restricted Project
HsiangKai added a comment to D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics..

Is this idea that this will later be "automatically" applied to builtins in riscv_vector.h?

Fri, Apr 16, 6:43 AM · Restricted Project
HsiangKai added inline comments to D100618: [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte..
Fri, Apr 16, 12:59 AM · Restricted Project

Thu, Apr 15

HsiangKai added a comment to D100574: [RISCV][WIP] Fix missing emergency slots for scalable stack offsets.

Sorry for not upstreaming this fix when I found it. I am busy on testing/debugging our downstream version recently. I think you need to update several tests after we reserved two more scavenging slots.

Thu, Apr 15, 6:43 PM · Restricted Project
HsiangKai added inline comments to D100574: [RISCV][WIP] Fix missing emergency slots for scalable stack offsets.
Thu, Apr 15, 6:34 PM · Restricted Project
HsiangKai requested review of D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics..
Thu, Apr 15, 6:28 PM · Restricted Project

Mon, Apr 12

HsiangKai added inline comments to D100280: [RISCV] Implement COPY for Zvlsseg registers.
Mon, Apr 12, 2:45 AM · Restricted Project
HsiangKai accepted D100284: [RISCV] Precommit a test case that test accessing a fixed object when has rvv vector object existed.

LGTM.

Mon, Apr 12, 2:30 AM · Restricted Project

Sat, Apr 10

HsiangKai committed rG471ae42c04e4: [RISCV][Clang] Add RVV vleff intrinsic functions. (authored by HsiangKai).
[RISCV][Clang] Add RVV vleff intrinsic functions.
Sat, Apr 10, 2:26 AM
HsiangKai closed D99151: [RISCV][Clang] Add RVV vleff intrinsic functions..
Sat, Apr 10, 2:25 AM · Restricted Project
HsiangKai added a comment to D100115: [RISCV] Add missing part of instruction vmsge {u}. VX.

Do we need this case? Case 4 is any vd. It means (vd == v0) || (vd != v0), right? These two cases are already covered by case 2 and case 3.

I think this is the case that a temp register is provided and the destination isn't v0. The user probably should use case 2 by not providing the temp register. But if they give the temp register should we accept it and match the spec or error for the destination not being v0(what we currently do)?

If the destination is not v0, case 2 is better than case 4. There should be no need to provide the temp register. I think the case 4 is useful when we could not determine vd is v0 or not, but it should not be the case in AsmParser. The registers in MCInst should be physical registers.

What does the GNU assembler do?

Can someone write inline assembly that requires this? If they let the compiler allocate the registers for the inline assembly we would need to support any register.

Sat, Apr 10, 2:08 AM · Restricted Project

Fri, Apr 9

HsiangKai added a comment to D100115: [RISCV] Add missing part of instruction vmsge {u}. VX.

Do we need this case? Case 4 is any vd. It means (vd == v0) || (vd != v0), right? These two cases are already covered by case 2 and case 3.

I think this is the case that a temp register is provided and the destination isn't v0. The user probably should use case 2 by not providing the temp register. But if they give the temp register should we accept it and match the spec or error for the destination not being v0(what we currently do)?

Fri, Apr 9, 2:02 AM · Restricted Project
HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

Rebase.

Fri, Apr 9, 1:50 AM · Restricted Project
HsiangKai updated the diff for D99593: [Clang][RISCV] Implement vlseg builtins..

Address comments.

Fri, Apr 9, 1:46 AM · Restricted Project

Thu, Apr 8

HsiangKai added a comment to D100115: [RISCV] Add missing part of instruction vmsge {u}. VX.

Do we need this case? Case 4 is any vd. It means (vd == v0) || (vd != v0), right? These two cases are already covered by case 2 and case 3.

Thu, Apr 8, 11:40 PM · Restricted Project
HsiangKai added a reviewer for D100115: [RISCV] Add missing part of instruction vmsge {u}. VX: craig.topper.
Thu, Apr 8, 11:38 PM · Restricted Project
HsiangKai updated the diff for D97264: [RISCV] Define types for Zvlsseg..

Put element types in the macro and use them to create RecordType directly.

Thu, Apr 8, 11:23 PM · Restricted Project
HsiangKai added a comment to D97264: [RISCV] Define types for Zvlsseg..

I was under the impression we didn't want to use class-member access syntax for vector tuples (see https://github.com/riscv/rvv-intrinsic-doc/issues/17#issuecomment-628998077 ) so we don't need a record type, do we?

Perhaps it is possible to model them like opaque entities similar to what we do with RVV vectors where they are expanded in CodegenTypes.cpp?

Access to fields would have to be through intrinsics, though I think this didn't scale very well, did it?

Thu, Apr 8, 8:44 PM · Restricted Project

Wed, Apr 7

HsiangKai committed rGba72bdef3250: [RISCV] Add scalable offset under very large stack size. (authored by HsiangKai).
[RISCV] Add scalable offset under very large stack size.
Wed, Apr 7, 11:47 PM
HsiangKai committed rGb8cd6681156a: [NFC][RISCV] Add test for scalable offset under large stack size. (authored by HsiangKai).
[NFC][RISCV] Add test for scalable offset under large stack size.
Wed, Apr 7, 11:47 PM
HsiangKai closed D100035: [RISCV] Add scalable offset under very large stack size..
Wed, Apr 7, 11:47 PM · Restricted Project
HsiangKai closed D100084: [NFC][RISCV] Add test for scalable offset under large stack size..
Wed, Apr 7, 11:47 PM · Restricted Project
HsiangKai added a comment to D100035: [RISCV] Add scalable offset under very large stack size..

I think it makes sense to me, but it would be good to pre-commit this test to better see the fix.

Wed, Apr 7, 7:54 PM · Restricted Project
HsiangKai updated the diff for D100035: [RISCV] Add scalable offset under very large stack size..
Wed, Apr 7, 7:53 PM · Restricted Project
HsiangKai requested review of D100084: [NFC][RISCV] Add test for scalable offset under large stack size..
Wed, Apr 7, 7:52 PM · Restricted Project
HsiangKai requested review of D100035: [RISCV] Add scalable offset under very large stack size..
Wed, Apr 7, 6:53 AM · Restricted Project

Tue, Apr 6

HsiangKai accepted D99527: [RISCV][Clang] Add RVV Widening Integer Extension intrinsic functions..

LGTM.

Tue, Apr 6, 12:27 AM · Restricted Project
HsiangKai added inline comments to D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions..
Tue, Apr 6, 12:21 AM · Restricted Project

Mon, Apr 5

HsiangKai accepted D99923: [RISCV] Add helper function to share some of the code for isel of vector load/store intrinsics..

LGTM.

Mon, Apr 5, 11:55 PM · Restricted Project

Thu, Apr 1

HsiangKai accepted D99704: [RISCV] Fix handling of nxvXi64 vmsgt(u).vx intrinsics on RV32..

LGTM.

Thu, Apr 1, 9:25 AM · Restricted Project

Wed, Mar 31

HsiangKai updated the diff for D99592: [PoC][Clang] Use TypeSize instead of uint64_t for getTypeAllocSize()..

Address comments.

Wed, Mar 31, 9:56 PM · Restricted Project
HsiangKai updated the diff for D99590: [Clang] Do not use memcpy for scalable struct copy..

Address comments.

Wed, Mar 31, 8:02 PM · Restricted Project
HsiangKai updated the diff for D99482: [PoC][Clang][CodeGen] Do not use getelementptr for scalable struct..

Address comments.

Wed, Mar 31, 7:53 PM · Restricted Project
HsiangKai added a comment to D99482: [PoC][Clang][CodeGen] Do not use getelementptr for scalable struct..

Are there any tests for this?

Wed, Mar 31, 7:51 PM · Restricted Project
HsiangKai added inline comments to D99236: [RISCV] Turn splat shuffles of vector loads into scalar loads and a splat..
Wed, Mar 31, 7:22 PM · Restricted Project
HsiangKai added a comment to D99148: [RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat..

LGTM. Waiting for the consent of others.

Wed, Mar 31, 6:14 AM · Restricted Project
HsiangKai accepted D99317: [RISCV] Add RISCVISD opcodes for CLZW and CTZW..

LGTM.

Wed, Mar 31, 2:35 AM · Restricted Project
HsiangKai accepted D99637: [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate.

LGTM.

Wed, Mar 31, 2:06 AM · Restricted Project

Tue, Mar 30

HsiangKai accepted D99631: [RISCV] Refine pre-define macro tests.

LGTM.

Tue, Mar 30, 7:23 PM · Restricted Project
HsiangKai accepted D99610: [RISCV][Clang] Add all RVV Fixed-Point Arithmetic intrinsic functions..

LGTM.

Tue, Mar 30, 6:40 PM · Restricted Project
HsiangKai accepted D99528: [RISCV][Clang] Add more RVV Integer intrinsic functions..

LGTM.

Tue, Mar 30, 6:34 PM · Restricted Project
HsiangKai requested review of D99593: [Clang][RISCV] Implement vlseg builtins..
Tue, Mar 30, 6:59 AM · Restricted Project
HsiangKai updated the diff for D97264: [RISCV] Define types for Zvlsseg..
Tue, Mar 30, 6:58 AM · Restricted Project
HsiangKai requested review of D99592: [PoC][Clang] Use TypeSize instead of uint64_t for getTypeAllocSize()..
Tue, Mar 30, 6:57 AM · Restricted Project
HsiangKai requested review of D99590: [Clang] Do not use memcpy for scalable struct copy..
Tue, Mar 30, 6:54 AM · Restricted Project
HsiangKai updated the diff for D99482: [PoC][Clang][CodeGen] Do not use getelementptr for scalable struct..
Tue, Mar 30, 6:52 AM · Restricted Project
HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

Use TrailingObjects for MemberOffsets.

Tue, Mar 30, 6:50 AM · Restricted Project

Mon, Mar 29

HsiangKai committed rG5821a58d8e4c: [RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'. (authored by HsiangKai).
[RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'.
Mon, Mar 29, 6:49 PM
HsiangKai closed D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'..
Mon, Mar 29, 6:49 PM · Restricted Project
HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

Fix build fail.

Mon, Mar 29, 6:22 PM · Restricted Project
HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..
  • Add an assertion to check if it is a scalable struct type before creating GEP instructions.
  • Address comments.
Mon, Mar 29, 3:06 PM · Restricted Project
HsiangKai added a comment to D99492: [RISCV] "V" Extention coming with "F" "D" "Zfh" Extentions.

There is no such implication in the V specification. See https://github.com/riscv/riscv-v-spec/issues/608.

Mon, Mar 29, 6:47 AM · Restricted Project
HsiangKai updated the diff for D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'..

Use 'vr' for vector registers and 'vm' for vector mask registers.

Mon, Mar 29, 3:31 AM · Restricted Project
HsiangKai accepted D99367: [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register..

LGTM.

Mon, Mar 29, 12:45 AM · Restricted Project

Sun, Mar 28

HsiangKai requested review of D99482: [PoC][Clang][CodeGen] Do not use getelementptr for scalable struct..
Sun, Mar 28, 9:17 PM · Restricted Project
HsiangKai updated the diff for D99151: [RISCV][Clang] Add RVV vleff intrinsic functions..

Add back ASM tests.

Sun, Mar 28, 8:36 PM · Restricted Project

Sat, Mar 27

HsiangKai committed rGbc82e9bf25ab: [RISCV] Add vfabs.v pseudo instruction. (authored by HsiangKai).
[RISCV] Add vfabs.v pseudo instruction.
Sat, Mar 27, 8:34 PM
HsiangKai closed D99454: [RISCV] Add vfabs.v pseudo instruction..
Sat, Mar 27, 8:34 PM · Restricted Project
HsiangKai requested review of D99454: [RISCV] Add vfabs.v pseudo instruction..
Sat, Mar 27, 4:44 AM · Restricted Project
HsiangKai updated the diff for D99151: [RISCV][Clang] Add RVV vleff intrinsic functions..

Address comments.

Sat, Mar 27, 2:30 AM · Restricted Project
HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

Consider scalable struct types in passes processing StructType and remove TODO comments.

Sat, Mar 27, 1:35 AM · Restricted Project

Fri, Mar 26

HsiangKai accepted D99140: [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC.

LGTM.

Fri, Mar 26, 4:15 PM · Restricted Project

Wed, Mar 24

HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

Fix test failed.

Wed, Mar 24, 2:46 AM · Restricted Project
HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

Use TypeSize for offsets instead of StackOffset.

Wed, Mar 24, 12:10 AM · Restricted Project

Tue, Mar 23

HsiangKai updated the diff for D99151: [RISCV][Clang] Add RVV vleff intrinsic functions..

Refine implementation.

Tue, Mar 23, 7:20 PM · Restricted Project
HsiangKai added reviewers for D99151: [RISCV][Clang] Add RVV vleff intrinsic functions.: khchen, arcbbb.
Tue, Mar 23, 12:51 AM · Restricted Project
HsiangKai added reviewers for D99151: [RISCV][Clang] Add RVV vleff intrinsic functions.: liaolucy, frasercrmck.
Tue, Mar 23, 12:50 AM · Restricted Project
HsiangKai requested review of D99151: [RISCV][Clang] Add RVV vleff intrinsic functions..
Tue, Mar 23, 12:49 AM · Restricted Project

Mon, Mar 22

HsiangKai accepted D99053: [RISCV] Add scheduler classes to Zfh instructions..

We could have another patch to simplify WriteFMulSubxx and WriteFMulAddxx. This patch is LGTM.

Mon, Mar 22, 7:21 PM · Restricted Project
HsiangKai added inline comments to D99053: [RISCV] Add scheduler classes to Zfh instructions..
Mon, Mar 22, 7:01 PM · Restricted Project
HsiangKai accepted D99050: [RISCV] Remove unused SchedWrites WriteFConv32/WriteFConv64/WriteFMov32/WriteFMov64..

LGTM.

Mon, Mar 22, 7:00 PM · Restricted Project

Mar 18 2021

HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..
  • Change the return type of getSizeInBytes() to TypeSize.
  • Mark the places we need to take care.
Mar 18 2021, 8:07 PM · Restricted Project
HsiangKai committed rGaa8d33a6d634: [RISCV] Spilling for Zvlsseg registers. (authored by HsiangKai).
[RISCV] Spilling for Zvlsseg registers.
Mar 18 2021, 5:07 PM
HsiangKai closed D98629: [RISCV] Spilling for Zvlsseg registers..
Mar 18 2021, 5:07 PM · Restricted Project

Mar 16 2021

HsiangKai updated the diff for D98629: [RISCV] Spilling for Zvlsseg registers..

Address comments.

Mar 16 2021, 8:46 PM · Restricted Project

Mar 15 2021

HsiangKai updated the diff for D98629: [RISCV] Spilling for Zvlsseg registers..

Use more meaningful name for variables.

Mar 15 2021, 7:43 PM · Restricted Project
HsiangKai updated the diff for D98629: [RISCV] Spilling for Zvlsseg registers..

Use isRVVSpillForZvlsseg() to get NF and LMUL.

Mar 15 2021, 7:35 PM · Restricted Project
HsiangKai updated the diff for D98629: [RISCV] Spilling for Zvlsseg registers..

Update comments.

Mar 15 2021, 5:51 AM · Restricted Project
HsiangKai requested review of D98629: [RISCV] Spilling for Zvlsseg registers..
Mar 15 2021, 5:47 AM · Restricted Project
HsiangKai added a reviewer for D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.: kito-cheng.
Mar 15 2021, 5:45 AM · Restricted Project

Mar 14 2021

HsiangKai committed rGa81dff1e5839: [RISCV] Support inline asm for vector instructions. (authored by HsiangKai).
[RISCV] Support inline asm for vector instructions.
Mar 14 2021, 8:03 PM
HsiangKai closed D97480: [RISCV] Support inline asm for vector instructions..
Mar 14 2021, 8:03 PM · Restricted Project
HsiangKai requested review of D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'..
Mar 14 2021, 7:48 PM · Restricted Project

Mar 13 2021

HsiangKai added a comment to D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

This patch is a proof of concept patch. We should have a formal discussion about the idea before reviewing this patch.

Mar 13 2021, 5:24 AM · Restricted Project
HsiangKai retitled D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors. from [IR] Permit load/store/alloca for struct with the same scalable vectors. to [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..
Mar 13 2021, 5:17 AM · Restricted Project

Mar 9 2021

HsiangKai added inline comments to D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..
Mar 9 2021, 10:59 PM · Restricted Project
HsiangKai updated the diff for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors..

Add comments before getSizeInBytes() and remove compare operators in the StackOffset.

Mar 9 2021, 10:57 PM · Restricted Project
HsiangKai updated the diff for D97480: [RISCV] Support inline asm for vector instructions..

Revert to use target hooks.

Mar 9 2021, 9:12 AM · Restricted Project
HsiangKai added inline comments to D97480: [RISCV] Support inline asm for vector instructions..
Mar 9 2021, 9:00 AM · Restricted Project

Mar 8 2021

HsiangKai updated the diff for D98161: [NFC][IR] Replace isa<ScalableVectorType> with a predicator function..

Remove redundant predicator functions.

Mar 8 2021, 6:58 PM · Restricted Project
HsiangKai updated the diff for D97480: [RISCV] Support inline asm for vector instructions..

To select the correct types for values in GetRegistersForValue().

Mar 8 2021, 4:56 PM · Restricted Project
HsiangKai added a comment to D98161: [NFC][IR] Replace isa<ScalableVectorType> with a predicator function..

What does isScalableVectorType() provide over the previous isa<ScalableVectorType>? Especially since it still appears next to cast<FixedVectorType>

Mar 8 2021, 4:05 PM · Restricted Project
HsiangKai added reviewers for D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors.: lebedev.ri, david-arm.
Mar 8 2021, 1:55 PM · Restricted Project
HsiangKai updated the diff for D98161: [NFC][IR] Replace isa<ScalableVectorType> with a predicator function..

Separate the checking into isScalableVectorType() and isScalableType().

Mar 8 2021, 1:52 PM · Restricted Project
HsiangKai added a comment to D98161: [NFC][IR] Replace isa<ScalableVectorType> with a predicator function..

I'm not convinced this is correct.
For example, shufflevector only works on vectors, so i don't see why a "struct with scalable vector" is even relevant there.

Mar 8 2021, 1:33 PM · Restricted Project