Wed, Dec 4
Tue, Dec 3
One nit below.
Mon, Dec 2
Looks reasonable (haven't looked at the ARM part.)
The change in shrink wrapping doesn't look correct to me though. Is that particular change require?
Thu, Nov 21
Fri, Nov 15
Wed, Nov 13
Nov 6 2019
Nov 4 2019
Are you planning on fixing the regression in the near future? If so splitting the patches this way seems fine
@arsenm ping^2 on the AMDGPU test changes.
Nov 1 2019
Thanks for the test case!
Oct 31 2019
For the test case, couldn't you add a isVariadic instruction with different patterns in one of the TableGen test?
Looks sensible to me.
Oct 30 2019
Oct 29 2019
@arsenm ping on the AMDGPU test changes.
Oct 28 2019
Thanks Philip for double checking.
Oct 25 2019
Oct 24 2019
I found a latent bug that has now more chances to trigger with the relaxations that this patch brings.
I've updated the patch to fix the bug, but I have now a bunch of "regressions" on AMDGPU test cases because the fix is too conservative.
Is this still okay to land?
- Fix a latent bug
- Update AMDGPU tests
Oct 23 2019
- Remove ADJUSTxxx operations in the tests
Oct 22 2019
Oct 21 2019
Thanks for the quick review @arsenm!
Oct 18 2019
Oct 17 2019
- Replace some unsigned into Register
This was just a patch to illustrate a possible direction.
Oct 16 2019
- Remove asserts already covered by the verifier
- Put .getType calls into a variable.
- Replace check with an assertion
- Update comments with pre-conditions
- Use ArrayRef instead of const SmallVectorImpl&
- Add tests with pointer types.
Oct 11 2019
Oct 7 2019
Sep 19 2019
Sep 17 2019
Sep 12 2019
Sep 11 2019
Sep 6 2019
The swifterror test change in this patch is one example. Live ranges over function calls can be problematic if under register pressure, which can cause additional moves, if not spills. There are others of course
I don't think this patch is correct in the sense that having statepoints depend on GreedyRegAlloc is a non-starter.
Indeed, that means that now any configuration that doesn't use greedy reg alloc (like fast or basic reg alloc) will generate incorrect code with respect to state point spilling.
Sep 4 2019
Suggestion of a small refactoring below.
Aug 20 2019
Aug 19 2019
Aug 16 2019
Aug 13 2019
LGTM with a test case.
LGTM for the generic part.
Aug 1 2019
Jul 19 2019
Jul 8 2019
It was added by D46315
Remove loop entirely. Ultimately determineCalleeSaves adds everything from MCRegAliasIterator anyway
Jul 5 2019
Let's go with that for now with one caveat. Does the code build without ANDGPU?
I.e., does the callingconv enum get generated?
Jul 3 2019
Jul 2 2019
General direction LGTM but there's a bug in the current patch unless I am mistaken.
Jun 19 2019
I second Daniel's comment, this is RegBankSelect's job to do this choice and the Legalizer shouldn't need to know about f64 vs. s64.
Maybe adding an MCRegister that's nearly identical might be a future improvement? That way it could enforce MCRegister->Register is OK, but Register->MCRegister is not
Jun 18 2019
Thanks for doing this Matt, this is a long due clean-up.
I haven't looked carefully at all the changes, but the general direction LGTM.
Jun 17 2019
Those rules work when there's a load/store for every type but they run into unable-to-legalize if that's not the case.