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Modifiedllvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.cpp
Modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
Modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
Modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
Modifiedllvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
Modifiedllvm/test/CodeGen/AMDGPU/hard-clauses.mir
Modifiedllvm/test/CodeGen/AMDGPU/nsa-reassign.mir
Modifiedllvm/test/CodeGen/AMDGPU/release-vgprs.mir
Modifiedllvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
Modifiedllvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
Modifiedllvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
Modifiedllvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
Modifiedllvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
Modifiedllvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
Modifiedllvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
Modifiedllvm/test/CodeGen/AMDGPU/wqm.mir
Modifiedllvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll