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Modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
Modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
Modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
Modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Modifiedllvm/lib/Target/RISCV/RISCV.td
Modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
Addedllvm/lib/Target/RISCV/RISCVInstrFormatsV.td
Modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
Modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
Addedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
Modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
Modifiedllvm/lib/Target/RISCV/RISCVSchedRocket32.td
Modifiedllvm/lib/Target/RISCV/RISCVSchedRocket64.td
Modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
Modifiedllvm/lib/Target/RISCV/RISCVSystemOperands.td
Modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
Addedllvm/test/MC/RISCV/rvv/add.s
Addedllvm/test/MC/RISCV/rvv/and.s
Addedllvm/test/MC/RISCV/rvv/clip.s
Addedllvm/test/MC/RISCV/rvv/compare.s
Addedllvm/test/MC/RISCV/rvv/convert.s
Addedllvm/test/MC/RISCV/rvv/div.s
Addedllvm/test/MC/RISCV/rvv/fadd.s
Addedllvm/test/MC/RISCV/rvv/fcompare.s
Addedllvm/test/MC/RISCV/rvv/fdiv.s
Addedllvm/test/MC/RISCV/rvv/fmacc.s
Addedllvm/test/MC/RISCV/rvv/fminmax.s
Addedllvm/test/MC/RISCV/rvv/fmul.s
Addedllvm/test/MC/RISCV/rvv/fmv.s
Addedllvm/test/MC/RISCV/rvv/fothers.s
Addedllvm/test/MC/RISCV/rvv/freduction.s
Addedllvm/test/MC/RISCV/rvv/fsub.s
Addedllvm/test/MC/RISCV/rvv/invalid.s
Addedllvm/test/MC/RISCV/rvv/load.s
Addedllvm/test/MC/RISCV/rvv/macc.s
Addedllvm/test/MC/RISCV/rvv/mask.s
Addedllvm/test/MC/RISCV/rvv/minmax.s
Addedllvm/test/MC/RISCV/rvv/mul.s
Addedllvm/test/MC/RISCV/rvv/mv.s
Addedllvm/test/MC/RISCV/rvv/or.s
Addedllvm/test/MC/RISCV/rvv/others.s
Addedllvm/test/MC/RISCV/rvv/reduction.s
Addedllvm/test/MC/RISCV/rvv/shift.s
Addedllvm/test/MC/RISCV/rvv/sign-injection.s
Addedllvm/test/MC/RISCV/rvv/snippet.s
Addedllvm/test/MC/RISCV/rvv/store.s
Addedllvm/test/MC/RISCV/rvv/sub.s
Addedllvm/test/MC/RISCV/rvv/vsetvl.s
Addedllvm/test/MC/RISCV/rvv/xor.s