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Differential D43141 Diff 133923 llvm/trunk/test/CodeGen/X86/undef-ops.ll

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llvm/trunk/test/CodeGen/X86/undef-ops.ll

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72; CHECK-NEXT: retq 72​; CHECK-NEXT: retq
73 %r = mul i32 %x, undef 73​ %r = mul i32 %x, undef
74 ret i32 %r 74​ ret i32 %r
75} 75​}
76 76​
77define <4 x i32> @mul_undef_rhs_vec(<4 x i32> %x) { 77​define <4 x i32> @mul_undef_rhs_vec(<4 x i32> %x) {
78; CHECK-LABEL: mul_undef_rhs_vec: 78​; CHECK-LABEL: mul_undef_rhs_vec:
79; CHECK: # %bb.0: 79​; CHECK: # %bb.0:
80​; CHECK-NEXT: xorps %xmm0, %xmm0
80; CHECK-NEXT: retq 81​; CHECK-NEXT: retq
81 %r = mul <4 x i32> %x, undef 82​ %r = mul <4 x i32> %x, undef
82 ret <4 x i32> %r 83​ ret <4 x i32> %r
83} 84​}
84 85​
85define i32 @mul_undef_lhs(i32 %x) { 86​define i32 @mul_undef_lhs(i32 %x) {
86; CHECK-LABEL: mul_undef_lhs: 87​; CHECK-LABEL: mul_undef_lhs:
87; CHECK: # %bb.0: 88​; CHECK: # %bb.0:
88; CHECK-NEXT: xorl %eax, %eax 89​; CHECK-NEXT: xorl %eax, %eax
89; CHECK-NEXT: retq 90​; CHECK-NEXT: retq
90 %r = mul i32 undef, %x 91​ %r = mul i32 undef, %x
91 ret i32 %r 92​ ret i32 %r
92} 93​}
93 94​
94define <4 x i32> @mul_undef_lhs_vec(<4 x i32> %x) { 95​define <4 x i32> @mul_undef_lhs_vec(<4 x i32> %x) {
95; CHECK-LABEL: mul_undef_lhs_vec: 96​; CHECK-LABEL: mul_undef_lhs_vec:
96; CHECK: # %bb.0: 97​; CHECK: # %bb.0:
98​; CHECK-NEXT: xorps %xmm0, %xmm0
97; CHECK-NEXT: retq 99​; CHECK-NEXT: retq
98 %r = mul <4 x i32> undef, %x 100​ %r = mul <4 x i32> undef, %x
99 ret <4 x i32> %r 101​ ret <4 x i32> %r
100} 102​}
101 103​
102define i32 @sdiv_undef_rhs(i32 %x) { 104​define i32 @sdiv_undef_rhs(i32 %x) {
103; CHECK-LABEL: sdiv_undef_rhs: 105​; CHECK-LABEL: sdiv_undef_rhs:
104; CHECK: # %bb.0: 106​; CHECK: # %bb.0:
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122; CHECK-NEXT: retq 124​; CHECK-NEXT: retq
123 %r = sdiv i32 undef, %x 125​ %r = sdiv i32 undef, %x
124 ret i32 %r 126​ ret i32 %r
125} 127​}
126 128​
127define <4 x i32> @sdiv_undef_lhs_vec(<4 x i32> %x) { 129​define <4 x i32> @sdiv_undef_lhs_vec(<4 x i32> %x) {
128; CHECK-LABEL: sdiv_undef_lhs_vec: 130​; CHECK-LABEL: sdiv_undef_lhs_vec:
129; CHECK: # %bb.0: 131​; CHECK: # %bb.0:
132​; CHECK-NEXT: xorps %xmm0, %xmm0
130; CHECK-NEXT: retq 133​; CHECK-NEXT: retq
131 %r = sdiv <4 x i32> undef, %x 134​ %r = sdiv <4 x i32> undef, %x
132 ret <4 x i32> %r 135​ ret <4 x i32> %r
133} 136​}
134 137​
135define i32 @udiv_undef_rhs(i32 %x) { 138​define i32 @udiv_undef_rhs(i32 %x) {
136; CHECK-LABEL: udiv_undef_rhs: 139​; CHECK-LABEL: udiv_undef_rhs:
137; CHECK: # %bb.0: 140​; CHECK: # %bb.0:
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155; CHECK-NEXT: retq 158​; CHECK-NEXT: retq
156 %r = udiv i32 undef, %x 159​ %r = udiv i32 undef, %x
157 ret i32 %r 160​ ret i32 %r
158} 161​}
159 162​
160define <4 x i32> @udiv_undef_lhs_vec(<4 x i32> %x) { 163​define <4 x i32> @udiv_undef_lhs_vec(<4 x i32> %x) {
161; CHECK-LABEL: udiv_undef_lhs_vec: 164​; CHECK-LABEL: udiv_undef_lhs_vec:
162; CHECK: # %bb.0: 165​; CHECK: # %bb.0:
166​; CHECK-NEXT: xorps %xmm0, %xmm0
163; CHECK-NEXT: retq 167​; CHECK-NEXT: retq
164 %r = udiv <4 x i32> undef, %x 168​ %r = udiv <4 x i32> undef, %x
165 ret <4 x i32> %r 169​ ret <4 x i32> %r
166} 170​}
167 171​
168define i32 @srem_undef_rhs(i32 %x) { 172​define i32 @srem_undef_rhs(i32 %x) {
169; CHECK-LABEL: srem_undef_rhs: 173​; CHECK-LABEL: srem_undef_rhs:
170; CHECK: # %bb.0: 174​; CHECK: # %bb.0:
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188; CHECK-NEXT: retq 192​; CHECK-NEXT: retq
189 %r = srem i32 undef, %x 193​ %r = srem i32 undef, %x
190 ret i32 %r 194​ ret i32 %r
191} 195​}
192 196​
193define <4 x i32> @srem_undef_lhs_vec(<4 x i32> %x) { 197​define <4 x i32> @srem_undef_lhs_vec(<4 x i32> %x) {
194; CHECK-LABEL: srem_undef_lhs_vec: 198​; CHECK-LABEL: srem_undef_lhs_vec:
195; CHECK: # %bb.0: 199​; CHECK: # %bb.0:
200​; CHECK-NEXT: xorps %xmm0, %xmm0
196; CHECK-NEXT: retq 201​; CHECK-NEXT: retq
197 %r = srem <4 x i32> undef, %x 202​ %r = srem <4 x i32> undef, %x
198 ret <4 x i32> %r 203​ ret <4 x i32> %r
199} 204​}
200 205​
201define i32 @urem_undef_rhs(i32 %x) { 206​define i32 @urem_undef_rhs(i32 %x) {
202; CHECK-LABEL: urem_undef_rhs: 207​; CHECK-LABEL: urem_undef_rhs:
203; CHECK: # %bb.0: 208​; CHECK: # %bb.0:
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221; CHECK-NEXT: retq 226​; CHECK-NEXT: retq
222 %r = urem i32 undef, %x 227​ %r = urem i32 undef, %x
223 ret i32 %r 228​ ret i32 %r
224} 229​}
225 230​
226define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) { 231​define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) {
227; CHECK-LABEL: urem_undef_lhs_vec: 232​; CHECK-LABEL: urem_undef_lhs_vec:
228; CHECK: # %bb.0: 233​; CHECK: # %bb.0:
234​; CHECK-NEXT: xorps %xmm0, %xmm0
229; CHECK-NEXT: retq 235​; CHECK-NEXT: retq
230 %r = urem <4 x i32> undef, %x 236​ %r = urem <4 x i32> undef, %x
231 ret <4 x i32> %r 237​ ret <4 x i32> %r
232} 238​}
233 239​
234define i32 @ashr_undef_rhs(i32 %x) { 240​define i32 @ashr_undef_rhs(i32 %x) {
235; CHECK-LABEL: ashr_undef_rhs: 241​; CHECK-LABEL: ashr_undef_rhs:
236; CHECK: # %bb.0: 242​; CHECK: # %bb.0:
237; CHECK-NEXT: movl %edi, %eax ​
238; CHECK-NEXT: retq 243​; CHECK-NEXT: retq
239 %r = ashr i32 %x, undef 244​ %r = ashr i32 %x, undef
240 ret i32 %r 245​ ret i32 %r
241} 246​}
242 247​
243define <4 x i32> @ashr_undef_rhs_vec(<4 x i32> %x) { 248​define <4 x i32> @ashr_undef_rhs_vec(<4 x i32> %x) {
244; CHECK-LABEL: ashr_undef_rhs_vec: 249​; CHECK-LABEL: ashr_undef_rhs_vec:
245; CHECK: # %bb.0: 250​; CHECK: # %bb.0:
246; CHECK-NEXT: retq 251​; CHECK-NEXT: retq
247 %r = ashr <4 x i32> %x, undef 252​ %r = ashr <4 x i32> %x, undef
248 ret <4 x i32> %r 253​ ret <4 x i32> %r
249} 254​}
250 255​
251define i32 @ashr_undef_lhs(i32 %x) { 256​define i32 @ashr_undef_lhs(i32 %x) {
252; CHECK-LABEL: ashr_undef_lhs: 257​; CHECK-LABEL: ashr_undef_lhs:
253; CHECK: # %bb.0: 258​; CHECK: # %bb.0:
259​; CHECK-NEXT: xorl %eax, %eax
254; CHECK-NEXT: retq 260​; CHECK-NEXT: retq
255 %r = ashr i32 undef, %x 261​ %r = ashr i32 undef, %x
256 ret i32 %r 262​ ret i32 %r
257} 263​}
258 264​
259define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) { 265​define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) {
260; CHECK-LABEL: ashr_undef_lhs_vec: 266​; CHECK-LABEL: ashr_undef_lhs_vec:
261; CHECK: # %bb.0: 267​; CHECK: # %bb.0:
268​; CHECK-NEXT: xorps %xmm0, %xmm0
262; CHECK-NEXT: retq 269​; CHECK-NEXT: retq
263 %r = ashr <4 x i32> undef, %x 270​ %r = ashr <4 x i32> undef, %x
264 ret <4 x i32> %r 271​ ret <4 x i32> %r
265} 272​}
266 273​
267define i32 @lshr_undef_rhs(i32 %x) { 274​define i32 @lshr_undef_rhs(i32 %x) {
268; CHECK-LABEL: lshr_undef_rhs: 275​; CHECK-LABEL: lshr_undef_rhs:
269; CHECK: # %bb.0: 276​; CHECK: # %bb.0:
270; CHECK-NEXT: xorl %eax, %eax ​
271; CHECK-NEXT: retq 277​; CHECK-NEXT: retq
272 %r = lshr i32 %x, undef 278​ %r = lshr i32 %x, undef
273 ret i32 %r 279​ ret i32 %r
274} 280​}
275 281​
276define <4 x i32> @lshr_undef_rhs_vec(<4 x i32> %x) { 282​define <4 x i32> @lshr_undef_rhs_vec(<4 x i32> %x) {
277; CHECK-LABEL: lshr_undef_rhs_vec: 283​; CHECK-LABEL: lshr_undef_rhs_vec:
278; CHECK: # %bb.0: 284​; CHECK: # %bb.0:
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288; CHECK-NEXT: retq 294​; CHECK-NEXT: retq
289 %r = lshr i32 undef, %x 295​ %r = lshr i32 undef, %x
290 ret i32 %r 296​ ret i32 %r
291} 297​}
292 298​
293define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) { 299​define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) {
294; CHECK-LABEL: lshr_undef_lhs_vec: 300​; CHECK-LABEL: lshr_undef_lhs_vec:
295; CHECK: # %bb.0: 301​; CHECK: # %bb.0:
302​; CHECK-NEXT: xorps %xmm0, %xmm0
296; CHECK-NEXT: retq 303​; CHECK-NEXT: retq
297 %r = lshr <4 x i32> undef, %x 304​ %r = lshr <4 x i32> undef, %x
298 ret <4 x i32> %r 305​ ret <4 x i32> %r
299} 306​}
300 307​
301define i32 @shl_undef_rhs(i32 %x) { 308​define i32 @shl_undef_rhs(i32 %x) {
302; CHECK-LABEL: shl_undef_rhs: 309​; CHECK-LABEL: shl_undef_rhs:
303; CHECK: # %bb.0: 310​; CHECK: # %bb.0:
304; CHECK-NEXT: xorl %eax, %eax ​
305; CHECK-NEXT: retq 311​; CHECK-NEXT: retq
306 %r = shl i32 %x, undef 312​ %r = shl i32 %x, undef
307 ret i32 %r 313​ ret i32 %r
308} 314​}
309 315​
310define <4 x i32> @shl_undef_rhs_vec(<4 x i32> %x) { 316​define <4 x i32> @shl_undef_rhs_vec(<4 x i32> %x) {
311; CHECK-LABEL: shl_undef_rhs_vec: 317​; CHECK-LABEL: shl_undef_rhs_vec:
312; CHECK: # %bb.0: 318​; CHECK: # %bb.0:
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322; CHECK-NEXT: retq 328​; CHECK-NEXT: retq
323 %r = shl i32 undef, %x 329​ %r = shl i32 undef, %x
324 ret i32 %r 330​ ret i32 %r
325} 331​}
326 332​
327define <4 x i32> @shl_undef_lhs_vec(<4 x i32> %x) { 333​define <4 x i32> @shl_undef_lhs_vec(<4 x i32> %x) {
328; CHECK-LABEL: shl_undef_lhs_vec: 334​; CHECK-LABEL: shl_undef_lhs_vec:
329; CHECK: # %bb.0: 335​; CHECK: # %bb.0:
336​; CHECK-NEXT: xorps %xmm0, %xmm0
330; CHECK-NEXT: retq 337​; CHECK-NEXT: retq
331 %r = shl <4 x i32> undef, %x 338​ %r = shl <4 x i32> undef, %x
332 ret <4 x i32> %r 339​ ret <4 x i32> %r
333} 340​}
334 341​
335define i32 @and_undef_rhs(i32 %x) { 342​define i32 @and_undef_rhs(i32 %x) {
336; CHECK-LABEL: and_undef_rhs: 343​; CHECK-LABEL: and_undef_rhs:
337; CHECK: # %bb.0: 344​; CHECK: # %bb.0:
338; CHECK-NEXT: xorl %eax, %eax 345​; CHECK-NEXT: xorl %eax, %eax
339; CHECK-NEXT: retq 346​; CHECK-NEXT: retq
340 %r = and i32 %x, undef 347​ %r = and i32 %x, undef
341 ret i32 %r 348​ ret i32 %r
342} 349​}
343 350​
344define <4 x i32> @and_undef_rhs_vec(<4 x i32> %x) { 351​define <4 x i32> @and_undef_rhs_vec(<4 x i32> %x) {
345; CHECK-LABEL: and_undef_rhs_vec: 352​; CHECK-LABEL: and_undef_rhs_vec:
346; CHECK: # %bb.0: 353​; CHECK: # %bb.0:
354​; CHECK-NEXT: xorps %xmm0, %xmm0
347; CHECK-NEXT: retq 355​; CHECK-NEXT: retq
348 %r = and <4 x i32> %x, undef 356​ %r = and <4 x i32> %x, undef
349 ret <4 x i32> %r 357​ ret <4 x i32> %r
350} 358​}
351 359​
352define i32 @and_undef_lhs(i32 %x) { 360​define i32 @and_undef_lhs(i32 %x) {
353; CHECK-LABEL: and_undef_lhs: 361​; CHECK-LABEL: and_undef_lhs:
354; CHECK: # %bb.0: 362​; CHECK: # %bb.0:
355; CHECK-NEXT: xorl %eax, %eax 363​; CHECK-NEXT: xorl %eax, %eax
356; CHECK-NEXT: retq 364​; CHECK-NEXT: retq
357 %r = and i32 undef, %x 365​ %r = and i32 undef, %x
358 ret i32 %r 366​ ret i32 %r
359} 367​}
360 368​
361define <4 x i32> @and_undef_lhs_vec(<4 x i32> %x) { 369​define <4 x i32> @and_undef_lhs_vec(<4 x i32> %x) {
362; CHECK-LABEL: and_undef_lhs_vec: 370​; CHECK-LABEL: and_undef_lhs_vec:
363; CHECK: # %bb.0: 371​; CHECK: # %bb.0:
372​; CHECK-NEXT: xorps %xmm0, %xmm0
364; CHECK-NEXT: retq 373​; CHECK-NEXT: retq
365 %r = and <4 x i32> undef, %x 374​ %r = and <4 x i32> undef, %x
366 ret <4 x i32> %r 375​ ret <4 x i32> %r
367} 376​}
368 377​
369define i32 @or_undef_rhs(i32 %x) { 378​define i32 @or_undef_rhs(i32 %x) {
370; CHECK-LABEL: or_undef_rhs: 379​; CHECK-LABEL: or_undef_rhs:
371; CHECK: # %bb.0: 380​; CHECK: # %bb.0:
372; CHECK-NEXT: movl $-1, %eax 381​; CHECK-NEXT: movl $-1, %eax
373; CHECK-NEXT: retq 382​; CHECK-NEXT: retq
374 %r = or i32 %x, undef 383​ %r = or i32 %x, undef
375 ret i32 %r 384​ ret i32 %r
376} 385​}
377 386​
378define <4 x i32> @or_undef_rhs_vec(<4 x i32> %x) { 387​define <4 x i32> @or_undef_rhs_vec(<4 x i32> %x) {
379; CHECK-LABEL: or_undef_rhs_vec: 388​; CHECK-LABEL: or_undef_rhs_vec:
380; CHECK: # %bb.0: 389​; CHECK: # %bb.0:
390​; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
381; CHECK-NEXT: retq 391​; CHECK-NEXT: retq
382 %r = or <4 x i32> %x, undef 392​ %r = or <4 x i32> %x, undef
383 ret <4 x i32> %r 393​ ret <4 x i32> %r
384} 394​}
385 395​
386define i32 @or_undef_lhs(i32 %x) { 396​define i32 @or_undef_lhs(i32 %x) {
387; CHECK-LABEL: or_undef_lhs: 397​; CHECK-LABEL: or_undef_lhs:
388; CHECK: # %bb.0: 398​; CHECK: # %bb.0:
389; CHECK-NEXT: movl $-1, %eax 399​; CHECK-NEXT: movl $-1, %eax
390; CHECK-NEXT: retq 400​; CHECK-NEXT: retq
391 %r = or i32 undef, %x 401​ %r = or i32 undef, %x
392 ret i32 %r 402​ ret i32 %r
393} 403​}
394 404​
395define <4 x i32> @or_undef_lhs_vec(<4 x i32> %x) { 405​define <4 x i32> @or_undef_lhs_vec(<4 x i32> %x) {
396; CHECK-LABEL: or_undef_lhs_vec: 406​; CHECK-LABEL: or_undef_lhs_vec:
397; CHECK: # %bb.0: 407​; CHECK: # %bb.0:
408​; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
398; CHECK-NEXT: retq 409​; CHECK-NEXT: retq
399 %r = or <4 x i32> undef, %x 410​ %r = or <4 x i32> undef, %x
400 ret <4 x i32> %r 411​ ret <4 x i32> %r
401} 412​}
402 413​
403define i32 @xor_undef_rhs(i32 %x) { 414​define i32 @xor_undef_rhs(i32 %x) {
404; CHECK-LABEL: xor_undef_rhs: 415​; CHECK-LABEL: xor_undef_rhs:
405; CHECK: # %bb.0: 416​; CHECK: # %bb.0:
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