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llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
| Show First 20 Lines • Show All 2,759 Lines • ▼ Show 20 Lines | if (Subtarget->isThumb()) { | ||||
| CurDAG->getRegister(0, MVT::i32) }; | CurDAG->getRegister(0, MVT::i32) }; | ||||
| ReplaceNode(N, CurDAG->getMachineNode( | ReplaceNode(N, CurDAG->getMachineNode( | ||||
| Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, | Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, | ||||
| MVT::i32, MVT::i32, Ops)); | MVT::i32, MVT::i32, Ops)); | ||||
| return; | return; | ||||
| } | } | ||||
| } | } | ||||
| case ARMISD::SUBE: { | case ARMISD::SUBE: { | ||||
| if (!Subtarget->hasV6Ops()) | if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) | ||||
| break; | break; | ||||
| // Look for a pattern to match SMMLS | // Look for a pattern to match SMMLS | ||||
| // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b)))) | // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b)))) | ||||
| if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI || | if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI || | ||||
| N->getOperand(2).getOpcode() != ARMISD::SUBC || | N->getOperand(2).getOpcode() != ARMISD::SUBC || | ||||
| !SDValue(N, 1).use_empty()) | !SDValue(N, 1).use_empty()) | ||||
| break; | break; | ||||
| ▲ Show 20 Lines • Show All 1,332 Lines • Show Last 20 Lines | |||||