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# llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

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Show First 20 Lines • Show All 35990 Lines • ▼ Show 20 Line(s) | 35900 | static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG, | |||
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35991 | // On pre-AVX512 targets, split into 256-bit nodes of | 35991 | // On pre-AVX512 targets, split into 256-bit nodes of | ||

35992 | // ISD::*_EXTEND_VECTOR_INREG. | 35992 | // ISD::*_EXTEND_VECTOR_INREG. | ||

35993 | if (!Subtarget.hasAVX512() && !(VT.getSizeInBits() % 256)) | 35993 | if (!Subtarget.hasAVX512() && !(VT.getSizeInBits() % 256)) | ||

35994 | return SplitAndExtendInReg(256); | 35994 | return SplitAndExtendInReg(256); | ||

35995 | 35995 | | |||

35996 | return SDValue(); | 35996 | return SDValue(); | ||

35997 | } | 35997 | } | ||

35998 | 35998 | | |||

35999 | // Attempt to combine a (sext/zext (setcc)) to a setcc with a xmm/ymm/zmm | ||||

36000 | // result type. | ||||

36001 | static SDValue combineExtSetcc(SDNode *N, SelectionDAG &DAG, | ||||

36002 | const X86Subtarget &Subtarget) { | ||||

36003 | SDValue N0 = N->getOperand(0); | ||||

36004 | EVT VT = N->getValueType(0); | ||||

36005 | SDLoc dl(N); | ||||

36006 | | ||||

36007 | // Only do this combine with AVX512 for vector extends. | ||||

36008 | if (!Subtarget.hasAVX512() || !VT.isVector() || N0->getOpcode() != ISD::SETCC) | ||||

36009 | return SDValue(); | ||||

36010 | | ||||

36011 | // Only combine legal element types. | ||||

36012 | EVT SVT = VT.getVectorElementType(); | ||||

36013 | if (SVT != MVT::i8 && SVT != MVT::i16 && SVT != MVT::i32 && | ||||

36014 | SVT != MVT::i64 && SVT != MVT::f32 && SVT != MVT::f64) | ||||

36015 | return SDValue(); | ||||

36016 | | ||||

36017 | // We can only do this if the vector size in 256 bits or less. | ||||

36018 | unsigned Size = VT.getSizeInBits(); | ||||

36019 | if (Size > 256) | ||||

36020 | return SDValue(); | ||||

36021 | | ||||

36022 | // Don't fold if the condition code can't be handled by PCMPEQ/PCMPGT since | ||||

36023 | // that's the only integer compares with we have. | ||||

36024 | ISD::CondCode CC = cast<CondCodeSDNode>(N0->getOperand(2))->get(); | ||||

36025 | if (ISD::isUnsignedIntSetCC(CC) || CC == ISD::SETLE || CC == ISD::SETGE || | ||||

36026 | CC == ISD::SETNE) | ||||

36027 | return SDValue(); | ||||

36028 | | ||||

36029 | // Only do this combine if the extension will be fully consumed by the setcc. | ||||

36030 | EVT N00VT = N0.getOperand(0).getValueType(); | ||||

36031 | EVT MatchingVecType = N00VT.changeVectorElementTypeToInteger(); | ||||

36032 | if (Size != MatchingVecType.getSizeInBits()) | ||||

36033 | return SDValue(); | ||||

36034 | | ||||

36035 | return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); | ||||

36036 | } | ||||

36037 | | ||||

35999 | static SDValue combineSext(SDNode *N, SelectionDAG &DAG, | 36038 | static SDValue combineSext(SDNode *N, SelectionDAG &DAG, | ||

36000 | TargetLowering::DAGCombinerInfo &DCI, | 36039 | TargetLowering::DAGCombinerInfo &DCI, | ||

36001 | const X86Subtarget &Subtarget) { | 36040 | const X86Subtarget &Subtarget) { | ||

36002 | SDValue N0 = N->getOperand(0); | 36041 | SDValue N0 = N->getOperand(0); | ||

36003 | EVT VT = N->getValueType(0); | 36042 | EVT VT = N->getValueType(0); | ||

36004 | EVT InVT = N0.getValueType(); | 36043 | EVT InVT = N0.getValueType(); | ||

36005 | SDLoc DL(N); | 36044 | SDLoc DL(N); | ||

36006 | 36045 | | |||

36007 | if (SDValue DivRem8 = getDivRem8(N, DAG)) | 36046 | if (SDValue DivRem8 = getDivRem8(N, DAG)) | ||

36008 | return DivRem8; | 36047 | return DivRem8; | ||

36009 | 36048 | | |||

36010 | if (SDValue NewCMov = combineToExtendCMOV(N, DAG)) | 36049 | if (SDValue NewCMov = combineToExtendCMOV(N, DAG)) | ||

36011 | return NewCMov; | 36050 | return NewCMov; | ||

36012 | 36051 | | |||

36013 | if (!DCI.isBeforeLegalizeOps()) | 36052 | if (!DCI.isBeforeLegalizeOps()) | ||

36014 | return SDValue(); | 36053 | return SDValue(); | ||

36015 | 36054 | | |||

36055 | if (SDValue V = combineExtSetcc(N, DAG, Subtarget)) | ||||

36056 | return V; | ||||

36057 | | ||||

36016 | if (InVT == MVT::i1 && N0.getOpcode() == ISD::XOR && | 36058 | if (InVT == MVT::i1 && N0.getOpcode() == ISD::XOR && | ||

36017 | isAllOnesConstant(N0.getOperand(1)) && N0.hasOneUse()) { | 36059 | isAllOnesConstant(N0.getOperand(1)) && N0.hasOneUse()) { | ||

36018 | // Invert and sign-extend a boolean is the same as zero-extend and subtract | 36060 | // Invert and sign-extend a boolean is the same as zero-extend and subtract | ||

36019 | // 1 because 0 becomes -1 and 1 becomes 0. The subtract is efficiently | 36061 | // 1 because 0 becomes -1 and 1 becomes 0. The subtract is efficiently | ||

36020 | // lowered with an LEA or a DEC. This is the same as: select Bool, 0, -1. | 36062 | // lowered with an LEA or a DEC. This is the same as: select Bool, 0, -1. | ||

36021 | // sext (xor Bool, -1) --> sub (zext Bool), 1 | 36063 | // sext (xor Bool, -1) --> sub (zext Bool), 1 | ||

36022 | SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); | 36064 | SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); | ||

36023 | return DAG.getNode(ISD::SUB, DL, VT, Zext, DAG.getConstant(1, DL, VT)); | 36065 | return DAG.getNode(ISD::SUB, DL, VT, Zext, DAG.getConstant(1, DL, VT)); | ||

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