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lib/Target/NVPTX/NVPTXRegisterInfo.td
| Show All 19 Lines | |||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // Registers | // Registers | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // Special Registers used as stack pointer | // Special Registers used as stack pointer | ||||
| def VRFrame : NVPTXReg<"%SP">; | def VRFrame : NVPTXReg<"%SP">; | ||||
| def VRFrameLocal : NVPTXReg<"%SPL">; | def VRFrameLocal : NVPTXReg<"%SPL">; | ||||
| def VRShared : NVPTXReg<"%SPS">; | |||||
| def VRFrameShared : NVPTXReg<"%SPSH">; | |||||
| // Special Registers used as the stack | // Special Registers used as the stack | ||||
| def VRDepot : NVPTXReg<"%Depot">; | def VRDepot : NVPTXReg<"%Depot">; | ||||
| def VRSharedDepot : NVPTXReg<"%SharedDepot">; | |||||
| // We use virtual registers, but define a few physical registers here to keep | // We use virtual registers, but define a few physical registers here to keep | ||||
| // SDAG and the MachineInstr layers happy. | // SDAG and the MachineInstr layers happy. | ||||
| foreach i = 0-4 in { | foreach i = 0-4 in { | ||||
| def P#i : NVPTXReg<"%p"#i>; // Predicate | def P#i : NVPTXReg<"%p"#i>; // Predicate | ||||
| def RS#i : NVPTXReg<"%rs"#i>; // 16-bit | def RS#i : NVPTXReg<"%rs"#i>; // 16-bit | ||||
| def R#i : NVPTXReg<"%r"#i>; // 32-bit | def R#i : NVPTXReg<"%r"#i>; // 32-bit | ||||
| def RL#i : NVPTXReg<"%rd"#i>; // 64-bit | def RL#i : NVPTXReg<"%rd"#i>; // 64-bit | ||||
| Show All 25 Lines | |||||
| def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>; | def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>; | ||||
| def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>; | def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>; | ||||
| def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>; | def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>; | ||||
| def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>; | def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>; | ||||
| def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>; | def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>; | ||||
| def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>; | def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>; | ||||
| // Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used. | // Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used. | ||||
| def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRFrameLocal, VRDepot, | def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRFrameLocal, VRDepot, | ||||
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| (sequence "ENVREG%u", 0, 31))>; | VRShared, VRFrameShared, VRSharedDepot, (sequence "ENVREG%u", 0, 31))>; | ||||
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