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# lib/Target/ARM/ARMInstrThumb2.td

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3877 | 3877 | | |||

3878 | // Pseudo isntruction that combines movs + predicated rsbmi | 3878 | // Pseudo isntruction that combines movs + predicated rsbmi | ||

3879 | // to implement integer ABS | 3879 | // to implement integer ABS | ||

3880 | let usesCustomInserter = 1, Defs = [CPSR] in { | 3880 | let usesCustomInserter = 1, Defs = [CPSR] in { | ||

3881 | def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src), | 3881 | def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src), | ||

3882 | NoItinerary, []>, Requires<[IsThumb2]>; | 3882 | NoItinerary, []>, Requires<[IsThumb2]>; | ||

3883 | } | 3883 | } | ||

3884 | 3884 | | |||

3885 | | ||||

3886 | //===----------------------------------------------------------------------===// | ||||

3887 | // Speculation barrier intrinsics | ||||

3888 | // | ||||

3889 | multiclass tNoSpeculateLoad<code TypeCheck> { | ||||

3890 | def _both_frag : PatFrag<(ops node:$ptr, node:$lower_bound, | ||||

3891 | node:$upper_bound, node:$failval, | ||||

3892 | node:$cmpptr), | ||||

3893 | (nospeculateload node:$ptr, node:$lower_bound, | ||||

3894 | node:$upper_bound, node:$failval, | ||||

3895 | node:$cmpptr), TypeCheck>; | ||||

3896 | def _nolower_frag : PatFrag<(ops node:$ptr, | ||||

3897 | node:$upper_bound, node:$failval, | ||||

3898 | node:$cmpptr), | ||||

3899 | (nospeculateload_nolower node:$ptr, | ||||

3900 | node:$upper_bound, node:$failval, | ||||

3901 | node:$cmpptr), TypeCheck>; | ||||

3902 | def _noupper_frag : PatFrag<(ops node:$ptr, node:$lower_bound, | ||||

3903 | node:$failval, node:$cmpptr), | ||||

3904 | (nospeculateload_noupper node:$ptr, node:$lower_bound, | ||||

3905 | node:$failval, | ||||

3906 | node:$cmpptr), TypeCheck>; | ||||

3907 | | ||||

3908 | let Defs = [CPSR], hasSideEffects = 1, isCodeGenOnly = 1, mayLoad = 1, | ||||

3909 | Constraints = "@earlyclobber $dst" in { | ||||

3910 | def _both : tPseudoInst<(outs tGPR:$dst), | ||||

3911 | (ins tGPR:$ptr, tGPR:$lower_bound, | ||||

3912 | tGPR:$upper_bound, rGPR:$failval, | ||||

3913 | tGPR:$cmpptr), | ||||

3914 | 18, IIC_iCMPr, | ||||

3915 | [(set tGPR:$dst, | ||||

3916 | (!cast<SDNode>(NAME # "_both_frag") tGPR:$ptr, tGPR:$lower_bound, | ||||

3917 | tGPR:$upper_bound, rGPR:$failval, | ||||

3918 | tGPR:$cmpptr))]>, | ||||

3919 | Sched<[]>; | ||||

3920 | def _nolower : | ||||

3921 | tPseudoInst<(outs tGPR:$dst), | ||||

3922 | (ins tGPR:$ptr, tGPR:$upper_bound, | ||||

3923 | rGPR:$failval, tGPR:$cmpptr), | ||||

3924 | 14, IIC_iCMPr, | ||||

3925 | [(set tGPR:$dst, | ||||

3926 | (!cast<SDNode>(NAME # "_nolower_frag") tGPR:$ptr, | ||||

3927 | tGPR:$upper_bound, rGPR:$failval, | ||||

3928 | tGPR:$cmpptr))]>, | ||||

3929 | Sched<[]>; | ||||

3930 | def _noupper : | ||||

3931 | tPseudoInst<(outs tGPR:$dst), | ||||

3932 | (ins tGPR:$ptr, tGPR:$lower_bound, | ||||

3933 | rGPR:$failval, tGPR:$cmpptr), | ||||

3934 | 14, IIC_iCMPr, | ||||

3935 | [(set tGPR:$dst, | ||||

3936 | (!cast<SDNode>(NAME # "_noupper_frag") tGPR:$ptr, tGPR:$lower_bound, | ||||

3937 | rGPR:$failval, | ||||

3938 | tGPR:$cmpptr))]>, | ||||

3939 | Sched<[]>; | ||||

3940 | } | ||||

3941 | } | ||||

3942 | | ||||

3943 | defm tNOSPECULATELOAD8 : tNoSpeculateLoad< | ||||

3944 | [{return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;}]>; | ||||

3945 | defm tNOSPECULATELOAD16 : tNoSpeculateLoad< | ||||

3946 | [{return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;}]>; | ||||

3947 | defm tNOSPECULATELOAD32 : tNoSpeculateLoad< | ||||

3948 | [{return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;}]>; | ||||

3949 | | ||||

3950 | let Defs = [CPSR], hasSideEffects = 1, isCodeGenOnly = 1, mayLoad = 1, | ||||

3951 | Constraints = "@earlyclobber $dstlo,@earlyclobber $dsthi" in { | ||||

3952 | def tNOSPECULATELOAD64_both : ARMPseudoInst<(outs rGPR:$dstlo, rGPR:$dsthi), | ||||

3953 | (ins tGPR:$ptr, tGPR:$lower_bound, | ||||

3954 | tGPR:$upper_bound, rGPR:$failvallo, rGPR:$failvalhi, | ||||

3955 | tGPR:$cmpptr), | ||||

3956 | 24, IIC_iCMPr, | ||||

3957 | []>, | ||||

3958 | Sched<[]>; | ||||

3959 | def tNOSPECULATELOAD64_nolower : ARMPseudoInst<(outs rGPR:$dstlo, rGPR:$dsthi), | ||||

3960 | (ins tGPR:$ptr, | ||||

3961 | tGPR:$upper_bound, rGPR:$failvallo, rGPR:$failvalhi, | ||||

3962 | tGPR:$cmpptr), | ||||

3963 | 20, IIC_iCMPr, | ||||

3964 | []>, | ||||

3965 | Sched<[]>; | ||||

3966 | def tNOSPECULATELOAD64_noupper : ARMPseudoInst<(outs rGPR:$dstlo, rGPR:$dsthi), | ||||

3967 | (ins tGPR:$ptr, | ||||

3968 | tGPR:$lower_bound, rGPR:$failvallo, rGPR:$failvalhi, | ||||

3969 | tGPR:$cmpptr), | ||||

3970 | 20, IIC_iCMPr, | ||||

3971 | []>, | ||||

3972 | Sched<[]>; | ||||

3973 | } | ||||

3974 | | ||||

3975 | | ||||

3885 | //===----------------------------------------------------------------------===// | 3976 | //===----------------------------------------------------------------------===// | ||

3886 | // Coprocessor load/store -- for disassembly only | 3977 | // Coprocessor load/store -- for disassembly only | ||

3887 | // | 3978 | // | ||

3888 | class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern> | 3979 | class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern> | ||

3889 | : T2I<oops, iops, NoItinerary, opc, asm, pattern> { | 3980 | : T2I<oops, iops, NoItinerary, opc, asm, pattern> { | ||

3890 | let Inst{31-28} = op31_28; | 3981 | let Inst{31-28} = op31_28; | ||

3891 | let Inst{27-25} = 0b110; | 3982 | let Inst{27-25} = 0b110; | ||

3892 | } | 3983 | } | ||

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