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lib/Basic/Targets/ARM.cpp
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| bool ARMTargetInfo::isCLZForZeroUndef() const { return false; } | bool ARMTargetInfo::isCLZForZeroUndef() const { return false; } | ||||
| TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const { | TargetInfo::BuiltinVaListKind ARMTargetInfo::getBuiltinVaListKind() const { | ||||
| return IsAAPCS | return IsAAPCS | ||||
| ? AAPCSABIBuiltinVaList | ? AAPCSABIBuiltinVaList | ||||
| : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList | : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList | ||||
| : TargetInfo::VoidPtrBuiltinVaList); | : TargetInfo::VoidPtrBuiltinVaList); | ||||
| } | } | ||||
| bool ARMTargetInfo::hasBuiltinLoadNoSpeculate() const { | |||||
| if (isThumb()) { | |||||
| if (supportsThumb2()) { | |||||
| if (ArchVersion >= 7) | |||||
| return true; | |||||
| } | |||||
| } else | |||||
| return true; | |||||
| return false; | |||||
| } | |||||
| const char *const ARMTargetInfo::GCCRegNames[] = { | const char *const ARMTargetInfo::GCCRegNames[] = { | ||||
| // Integer registers | // Integer registers | ||||
| "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", | ||||
| "r12", "sp", "lr", "pc", | "r12", "sp", "lr", "pc", | ||||
| // Float registers | // Float registers | ||||
| "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", | ||||
| "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", | "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", | ||||
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