Page MenuHomePhabricator
Differential D4637 Diff 11800 test/CodeGen/AArch64/arm64-scvt.ll

Changeset View

Standalone View

View Options

test/CodeGen/AArch64/arm64-scvt.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -march=arm64 -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -march=arm64 -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s
; rdar://13082402 ; rdar://13082402
define float @t1(i32* nocapture %src) nounwind ssp { define float @t1(i32* nocapture %src) nounwind ssp {
Context not available.
; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
; CHECK-NEXT: fmul s0, [[REG]], [[REG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
; CHECK-A57-LABEL: sfct1:
; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, #1]
; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
entry: entry:
%addr = getelementptr i8* %sp0, i64 1 %addr = getelementptr i8* %sp0, i64 1
%pix_sp0.0.copyload = load i8* %addr, align 1 %pix_sp0.0.copyload = load i8* %addr, align 1
Context not available.
; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
; CHECK-NEXT: fmul s0, [[REG]], [[REG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
; CHECK-A57-LABEL: sfct5:
; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, x1]
; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
entry: entry:
%addr = getelementptr i8* %sp0, i64 %offset %addr = getelementptr i8* %sp0, i64 %offset
%pix_sp0.0.copyload = load i8* %addr, align 1 %pix_sp0.0.copyload = load i8* %addr, align 1
Context not available.
; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
; CHECK-NEXT: fmul d0, [[REG]], [[REG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
; CHECK-A57-LABEL: sfct10:
; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, #2]
; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
entry: entry:
%addr = getelementptr i16* %sp0, i64 1 %addr = getelementptr i16* %sp0, i64 1
%pix_sp0.0.copyload = load i16* %addr, align 1 %pix_sp0.0.copyload = load i16* %addr, align 1
Context not available.
; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
; CHECK-NEXT: fmul d0, [[REG]], [[REG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
; CHECK-A57-LABEL: sfct14:
; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
entry: entry:
%addr = getelementptr i16* %sp0, i64 %offset %addr = getelementptr i16* %sp0, i64 %offset
%pix_sp0.0.copyload = load i16* %addr, align 1 %pix_sp0.0.copyload = load i16* %addr, align 1
Context not available.
; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
; CHECK-NEXT: fmul s0, [[REG]], [[REG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
; CHECK-A57-LABEL: sfct17:
; CHECK-A57: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
%bitcast = ptrtoint i8* %sp0 to i64 %bitcast = ptrtoint i8* %sp0 to i64
%add = add i64 %bitcast, -1 %add = add i64 %bitcast, -1
%addr = inttoptr i64 %add to i8* %addr = inttoptr i64 %add to i8*
Context not available.
; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0 ; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
; CHECK-NEXT: fmul d0, [[REG]], [[REG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
; CHECK-A57-LABEL: sfct22:
; CHECK-A57: ldursh w[[REGNUM:[0-9]+]], [x0, #1]
; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
%bitcast = ptrtoint i16* %sp0 to i64 %bitcast = ptrtoint i16* %sp0 to i64
%add = add i64 %bitcast, 1 %add = add i64 %bitcast, 1
%addr = inttoptr i64 %add to i16* %addr = inttoptr i64 %add to i16*
Context not available.