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lib/Target/AArch64/AArch64InstrInfo.td
| Context not available. | |||||
| AssemblerPredicate<"FeatureCRC", "crc">; | AssemblerPredicate<"FeatureCRC", "crc">; | ||||
| def IsLE : Predicate<"Subtarget->isLittleEndian()">; | def IsLE : Predicate<"Subtarget->isLittleEndian()">; | ||||
| def IsBE : Predicate<"!Subtarget->isLittleEndian()">; | def IsBE : Predicate<"!Subtarget->isLittleEndian()">; | ||||
| def IsCyclone : Predicate<"Subtarget->isCyclone()">; | |||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // AArch64-specific DAG Nodes. | // AArch64-specific DAG Nodes. | ||||
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| 0), | 0), | ||||
| dsub)), | dsub)), | ||||
| 0), | 0), | ||||
| ssub)))>, Requires<[NotForCodeSize]>; | ssub)))>, Requires<[NotForCodeSize, IsCyclone]>; | ||||
| def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext), | def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext), | ||||
| (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>; | (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>; | ||||
| Context not available. | |||||
| 0), | 0), | ||||
| dsub)), | dsub)), | ||||
| 0), | 0), | ||||
| dsub)))>, Requires<[NotForCodeSize]>; | dsub)))>, Requires<[NotForCodeSize, IsCyclone]>; | ||||
| def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), | def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), | ||||
| (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; | (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; | ||||
| def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), | def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), | ||||
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