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llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp
//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// | //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// | ||||
// | // | ||||
// The LLVM Compiler Infrastructure | // The LLVM Compiler Infrastructure | ||||
// | // | ||||
// This file is distributed under the University of Illinois Open Source | // This file is distributed under the University of Illinois Open Source | ||||
// License. See LICENSE.TXT for details. | // License. See LICENSE.TXT for details. | ||||
// | // | ||||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
// | // | ||||
// Implements the info about RISCV target spec. | // Implements the info about RISCV target spec. | ||||
// | // | ||||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
#include "RISCV.h" | |||||
#include "RISCVTargetMachine.h" | #include "RISCVTargetMachine.h" | ||||
#include "llvm/ADT/STLExtras.h" | #include "llvm/ADT/STLExtras.h" | ||||
#include "llvm/CodeGen/Passes.h" | #include "llvm/CodeGen/Passes.h" | ||||
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" | #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" | ||||
#include "llvm/CodeGen/TargetPassConfig.h" | #include "llvm/CodeGen/TargetPassConfig.h" | ||||
#include "llvm/IR/LegacyPassManager.h" | #include "llvm/IR/LegacyPassManager.h" | ||||
#include "llvm/Support/FormattedStream.h" | #include "llvm/Support/FormattedStream.h" | ||||
#include "llvm/Support/TargetRegistry.h" | #include "llvm/Support/TargetRegistry.h" | ||||
Show All 31 Lines | RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, | ||||
StringRef CPU, StringRef FS, | StringRef CPU, StringRef FS, | ||||
const TargetOptions &Options, | const TargetOptions &Options, | ||||
Optional<Reloc::Model> RM, | Optional<Reloc::Model> RM, | ||||
Optional<CodeModel::Model> CM, | Optional<CodeModel::Model> CM, | ||||
CodeGenOpt::Level OL, bool JIT) | CodeGenOpt::Level OL, bool JIT) | ||||
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, | : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, | ||||
getEffectiveRelocModel(TT, RM), | getEffectiveRelocModel(TT, RM), | ||||
getEffectiveCodeModel(CM), OL), | getEffectiveCodeModel(CM), OL), | ||||
TLOF(make_unique<TargetLoweringObjectFileELF>()) { | TLOF(make_unique<TargetLoweringObjectFileELF>()), | ||||
Subtarget(TT, CPU, FS, *this) { | |||||
initAsmInfo(); | initAsmInfo(); | ||||
} | } | ||||
namespace { | |||||
class RISCVPassConfig : public TargetPassConfig { | |||||
public: | |||||
RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) | |||||
: TargetPassConfig(TM, PM) {} | |||||
RISCVTargetMachine &getRISCVTargetMachine() const { | |||||
return getTM<RISCVTargetMachine>(); | |||||
} | |||||
bool addInstSelector() override; | |||||
}; | |||||
} | |||||
TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { | TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { | ||||
return new TargetPassConfig(*this, PM); | return new RISCVPassConfig(*this, PM); | ||||
} | |||||
bool RISCVPassConfig::addInstSelector() { | |||||
addPass(createRISCVISelDag(getRISCVTargetMachine())); | |||||
return false; | |||||
} | } |