Differential D29933 Diff 119619 llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp

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llvm/trunk/lib/Target/RISCV/RISCVTargetMachine.cpp

1	//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//	1		//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2	//	2		//
3	// The LLVM Compiler Infrastructure	3		// The LLVM Compiler Infrastructure
4	//	4		//
5	// This file is distributed under the University of Illinois Open Source	5		// This file is distributed under the University of Illinois Open Source
6	// License. See LICENSE.TXT for details.	6		// License. See LICENSE.TXT for details.
7	//	7		//
8	//===----------------------------------------------------------------------===//	8		//===----------------------------------------------------------------------===//
9	//	9		//
10	// Implements the info about RISCV target spec.	10		// Implements the info about RISCV target spec.
11	//	11		//
12	//===----------------------------------------------------------------------===//	12		//===----------------------------------------------------------------------===//
13		13
		14		#include "RISCV.h"
14	#include "RISCVTargetMachine.h"	15		#include "RISCVTargetMachine.h"
15	#include "llvm/ADT/STLExtras.h"	16		#include "llvm/ADT/STLExtras.h"
16	#include "llvm/CodeGen/Passes.h"	17		#include "llvm/CodeGen/Passes.h"
17	#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"	18		#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
18	#include "llvm/CodeGen/TargetPassConfig.h"	19		#include "llvm/CodeGen/TargetPassConfig.h"
19	#include "llvm/IR/LegacyPassManager.h"	20		#include "llvm/IR/LegacyPassManager.h"
20	#include "llvm/Support/FormattedStream.h"	21		#include "llvm/Support/FormattedStream.h"
21	#include "llvm/Support/TargetRegistry.h"	22		#include "llvm/Support/TargetRegistry.h"
Show All 31 Lines		53	RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
53	StringRef CPU, StringRef FS,	54		StringRef CPU, StringRef FS,
54	const TargetOptions &Options,	55		const TargetOptions &Options,
55	Optional<Reloc::Model> RM,	56		Optional<Reloc::Model> RM,
56	Optional<CodeModel::Model> CM,	57		Optional<CodeModel::Model> CM,
57	CodeGenOpt::Level OL, bool JIT)	58		CodeGenOpt::Level OL, bool JIT)
58	: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,	59		: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
59	getEffectiveRelocModel(TT, RM),	60		getEffectiveRelocModel(TT, RM),
60	getEffectiveCodeModel(CM), OL),	61		getEffectiveCodeModel(CM), OL),
61	TLOF(make_unique<TargetLoweringObjectFileELF>()) {	62		TLOF(make_unique<TargetLoweringObjectFileELF>()),
		63		Subtarget(TT, CPU, FS, *this) {
62	initAsmInfo();	64		initAsmInfo();
63	}	65		}
64		66
		67		namespace {
		68		class RISCVPassConfig : public TargetPassConfig {
		69		public:
		70		RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
		71		: TargetPassConfig(TM, PM) {}
		72
		73		RISCVTargetMachine &getRISCVTargetMachine() const {
		74		return getTM<RISCVTargetMachine>();
		75		}
		76
		77		bool addInstSelector() override;
		78		};
		79		}
		80
65	TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {	81		TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
66	return new TargetPassConfig(*this, PM);	82		return new RISCVPassConfig(*this, PM);
		83		}
		84
		85		bool RISCVPassConfig::addInstSelector() {
		86		addPass(createRISCVISelDag(getRISCVTargetMachine()));
		87
		88		return false;
67	}	89		}