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Differential D35844 Diff 119589 test/CodeGen/X86/vector-sext.ll

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test/CodeGen/X86/vector-sext.ll

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; AVX1-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1
; AVX1-NEXT: shlq $57, %rsi ; AVX1-NEXT: shlq $57, %rsi
; AVX1-NEXT: sarq $63, %rsi ; AVX1-NEXT: sarq $63, %rsi
; AVX1-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1
; AVX1-NEXT: shrq $7, %rbp ; AVX1-NEXT: shrq $7, %rbp
; AVX1-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: .Lcfi12:
; AVX1-NEXT: .cfi_def_cfa_offset 48
; AVX1-NEXT: popq %r12 ; AVX1-NEXT: popq %r12
; AVX1-NEXT: .Lcfi13:
; AVX1-NEXT: .cfi_def_cfa_offset 40
; AVX1-NEXT: popq %r13 ; AVX1-NEXT: popq %r13
; AVX1-NEXT: .Lcfi14:
; AVX1-NEXT: .cfi_def_cfa_offset 32
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: .Lcfi15:
; AVX1-NEXT: .cfi_def_cfa_offset 24
; AVX1-NEXT: popq %r15 ; AVX1-NEXT: popq %r15
; AVX1-NEXT: .Lcfi16:
; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi17:
; AVX1-NEXT: .cfi_def_cfa_offset 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: load_sext_16i1_to_16i16: ; AVX2-LABEL: load_sext_16i1_to_16i16:
; AVX2: # BB#0: # %entry ; AVX2: # BB#0: # %entry
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi0: ; AVX2-NEXT: .Lcfi0:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: pushq %r15 ; AVX2-NEXT: pushq %r15
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; AVX2-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1
; AVX2-NEXT: shlq $57, %rsi ; AVX2-NEXT: shlq $57, %rsi
; AVX2-NEXT: sarq $63, %rsi ; AVX2-NEXT: sarq $63, %rsi
; AVX2-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1
; AVX2-NEXT: shrq $7, %rbp ; AVX2-NEXT: shrq $7, %rbp
; AVX2-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: .Lcfi12:
; AVX2-NEXT: .cfi_def_cfa_offset 48
; AVX2-NEXT: popq %r12 ; AVX2-NEXT: popq %r12
; AVX2-NEXT: .Lcfi13:
; AVX2-NEXT: .cfi_def_cfa_offset 40
; AVX2-NEXT: popq %r13 ; AVX2-NEXT: popq %r13
; AVX2-NEXT: .Lcfi14:
; AVX2-NEXT: .cfi_def_cfa_offset 32
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: .Lcfi15:
; AVX2-NEXT: .cfi_def_cfa_offset 24
; AVX2-NEXT: popq %r15 ; AVX2-NEXT: popq %r15
; AVX2-NEXT: .Lcfi16:
; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi17:
; AVX2-NEXT: .cfi_def_cfa_offset 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: load_sext_16i1_to_16i16: ; AVX512F-LABEL: load_sext_16i1_to_16i16:
; AVX512F: # BB#0: # %entry ; AVX512F: # BB#0: # %entry
; AVX512F-NEXT: kmovw (%rdi), %k1 ; AVX512F-NEXT: kmovw (%rdi), %k1
; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
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; X32-SSE41-LABEL: sext_2i8_to_i32: ; X32-SSE41-LABEL: sext_2i8_to_i32:
; X32-SSE41: # BB#0: # %entry ; X32-SSE41: # BB#0: # %entry
; X32-SSE41-NEXT: pushl %eax ; X32-SSE41-NEXT: pushl %eax
; X32-SSE41-NEXT: .Lcfi0: ; X32-SSE41-NEXT: .Lcfi0:
; X32-SSE41-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE41-NEXT: .cfi_def_cfa_offset 8
; X32-SSE41-NEXT: pmovsxbw %xmm0, %xmm0 ; X32-SSE41-NEXT: pmovsxbw %xmm0, %xmm0
; X32-SSE41-NEXT: movd %xmm0, %eax ; X32-SSE41-NEXT: movd %xmm0, %eax
; X32-SSE41-NEXT: popl %ecx ; X32-SSE41-NEXT: popl %ecx
; X32-SSE41-NEXT: .Lcfi1:
; X32-SSE41-NEXT: .cfi_def_cfa_offset 4
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
entry: entry:
%Shuf = shufflevector <16 x i8> %A, <16 x i8> undef, <2 x i32> <i32 0, i32 1> %Shuf = shufflevector <16 x i8> %A, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
%Ex = sext <2 x i8> %Shuf to <2 x i16> %Ex = sext <2 x i8> %Shuf to <2 x i16>
%Bc = bitcast <2 x i16> %Ex to i32 %Bc = bitcast <2 x i16> %Ex to i32
ret i32 %Bc ret i32 %Bc
} }
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