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Differential D35844 Diff 119589 test/CodeGen/X86/merge-consecutive-loads-128.ll

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test/CodeGen/X86/merge-consecutive-loads-128.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: movl 16(%ecx), %edi ; X32-SSE1-NEXT: movl 16(%ecx), %edi
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %ecx, 12(%eax) ; X32-SSE1-NEXT: movl %ecx, 12(%eax)
; X32-SSE1-NEXT: movl %edi, 8(%eax) ; X32-SSE1-NEXT: movl %edi, 8(%eax)
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi4:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi5:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_2i64_i64_12: ; X32-SSE41-LABEL: merge_2i64_i64_12:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movups 8(%eax), %xmm0 ; X32-SSE41-NEXT: movups 8(%eax), %xmm0
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
%ptr0 = getelementptr inbounds i64, i64* %ptr, i64 1 %ptr0 = getelementptr inbounds i64, i64* %ptr, i64 1
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; AVX-LABEL: merge_4i32_i32_23u5: ; AVX-LABEL: merge_4i32_i32_23u5:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 8(%rdi), %xmm0 ; AVX-NEXT: vmovups 8(%rdi), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_23u5: ; X32-SSE1-LABEL: merge_4i32_i32_23u5:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi4: ; X32-SSE1-NEXT: .Lcfi6:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: .Lcfi5: ; X32-SSE1-NEXT: .Lcfi7:
; X32-SSE1-NEXT: .cfi_offset %esi, -8 ; X32-SSE1-NEXT: .cfi_offset %esi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: movl %ecx, 12(%eax) ; X32-SSE1-NEXT: movl %ecx, 12(%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi8:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_4i32_i32_23u5: ; X32-SSE41-LABEL: merge_4i32_i32_23u5:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movups 8(%eax), %xmm0 ; X32-SSE41-NEXT: movups 8(%eax), %xmm0
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 2 %ptr0 = getelementptr inbounds i32, i32* %ptr, i64 2
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; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 8(%rdi), %xmm0 ; AVX-NEXT: vmovups 8(%rdi), %xmm0
; AVX-NEXT: incl 8(%rdi) ; AVX-NEXT: incl 8(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc2: ; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc2:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi6: ; X32-SSE1-NEXT: .Lcfi9:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi7: ; X32-SSE1-NEXT: .Lcfi10:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi8: ; X32-SSE1-NEXT: .Lcfi11:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi9: ; X32-SSE1-NEXT: .Lcfi12:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%edx), %edi ; X32-SSE1-NEXT: leal 1(%edx), %edi
; X32-SSE1-NEXT: movl %edi, 8(%ecx) ; X32-SSE1-NEXT: movl %edi, 8(%ecx)
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: movl %ecx, 12(%eax) ; X32-SSE1-NEXT: movl %ecx, 12(%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi13:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi14:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_4i32_i32_23u5_inc2: ; X32-SSE41-LABEL: merge_4i32_i32_23u5_inc2:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movups 8(%eax), %xmm0 ; X32-SSE41-NEXT: movups 8(%eax), %xmm0
; X32-SSE41-NEXT: incl 8(%eax) ; X32-SSE41-NEXT: incl 8(%eax)
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
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; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 8(%rdi), %xmm0 ; AVX-NEXT: vmovups 8(%rdi), %xmm0
; AVX-NEXT: incl 12(%rdi) ; AVX-NEXT: incl 12(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc3: ; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc3:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi10: ; X32-SSE1-NEXT: .Lcfi15:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi11: ; X32-SSE1-NEXT: .Lcfi16:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi12: ; X32-SSE1-NEXT: .Lcfi17:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi13: ; X32-SSE1-NEXT: .Lcfi18:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%esi), %edi ; X32-SSE1-NEXT: leal 1(%esi), %edi
; X32-SSE1-NEXT: movl %edi, 12(%ecx) ; X32-SSE1-NEXT: movl %edi, 12(%ecx)
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: movl %ecx, 12(%eax) ; X32-SSE1-NEXT: movl %ecx, 12(%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi19:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi20:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_4i32_i32_23u5_inc3: ; X32-SSE41-LABEL: merge_4i32_i32_23u5_inc3:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movups 8(%eax), %xmm0 ; X32-SSE41-NEXT: movups 8(%eax), %xmm0
; X32-SSE41-NEXT: incl 12(%eax) ; X32-SSE41-NEXT: incl 12(%eax)
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
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; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: incl 16(%rdi) ; AVX-NEXT: incl 16(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc4: ; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc4:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi14: ; X32-SSE1-NEXT: .Lcfi21:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi15: ; X32-SSE1-NEXT: .Lcfi22:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi16: ; X32-SSE1-NEXT: .Lcfi23:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi17: ; X32-SSE1-NEXT: .Lcfi24:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 16(%ecx), %edx ; X32-SSE1-NEXT: movl 16(%ecx), %edx
; X32-SSE1-NEXT: movl 20(%ecx), %esi ; X32-SSE1-NEXT: movl 20(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%edx), %edi ; X32-SSE1-NEXT: leal 1(%edx), %edi
; X32-SSE1-NEXT: movl %edi, 16(%ecx) ; X32-SSE1-NEXT: movl %edi, 16(%ecx)
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: movl $0, 12(%eax) ; X32-SSE1-NEXT: movl $0, 12(%eax)
; X32-SSE1-NEXT: movl $0, 8(%eax) ; X32-SSE1-NEXT: movl $0, 8(%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi25:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi26:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_4i32_i32_45zz_inc4: ; X32-SSE41-LABEL: merge_4i32_i32_45zz_inc4:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X32-SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X32-SSE41-NEXT: incl 16(%eax) ; X32-SSE41-NEXT: incl 16(%eax)
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
Show All 19 Lines
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: incl 20(%rdi) ; AVX-NEXT: incl 20(%rdi)
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc5: ; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc5:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi18: ; X32-SSE1-NEXT: .Lcfi27:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi19: ; X32-SSE1-NEXT: .Lcfi28:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi20: ; X32-SSE1-NEXT: .Lcfi29:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi21: ; X32-SSE1-NEXT: .Lcfi30:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 16(%ecx), %edx ; X32-SSE1-NEXT: movl 16(%ecx), %edx
; X32-SSE1-NEXT: movl 20(%ecx), %esi ; X32-SSE1-NEXT: movl 20(%ecx), %esi
; X32-SSE1-NEXT: leal 1(%esi), %edi ; X32-SSE1-NEXT: leal 1(%esi), %edi
; X32-SSE1-NEXT: movl %edi, 20(%ecx) ; X32-SSE1-NEXT: movl %edi, 20(%ecx)
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: movl $0, 12(%eax) ; X32-SSE1-NEXT: movl $0, 12(%eax)
; X32-SSE1-NEXT: movl $0, 8(%eax) ; X32-SSE1-NEXT: movl $0, 8(%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi31:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi32:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_4i32_i32_45zz_inc5: ; X32-SSE41-LABEL: merge_4i32_i32_45zz_inc5:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X32-SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X32-SSE41-NEXT: incl 20(%eax) ; X32-SSE41-NEXT: incl 20(%eax)
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
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; AVX-LABEL: merge_8i16_i16_23u567u9: ; AVX-LABEL: merge_8i16_i16_23u567u9:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups 4(%rdi), %xmm0 ; AVX-NEXT: vmovups 4(%rdi), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_8i16_i16_23u567u9: ; X32-SSE1-LABEL: merge_8i16_i16_23u567u9:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi22: ; X32-SSE1-NEXT: .Lcfi33:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi23: ; X32-SSE1-NEXT: .Lcfi34:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi24: ; X32-SSE1-NEXT: .Lcfi35:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi25: ; X32-SSE1-NEXT: .Lcfi36:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 4(%ecx), %edx ; X32-SSE1-NEXT: movl 4(%ecx), %edx
; X32-SSE1-NEXT: movl 10(%ecx), %esi ; X32-SSE1-NEXT: movl 10(%ecx), %esi
; X32-SSE1-NEXT: movzwl 14(%ecx), %edi ; X32-SSE1-NEXT: movzwl 14(%ecx), %edi
; X32-SSE1-NEXT: movzwl 18(%ecx), %ecx ; X32-SSE1-NEXT: movzwl 18(%ecx), %ecx
; X32-SSE1-NEXT: movw %di, 10(%eax) ; X32-SSE1-NEXT: movw %di, 10(%eax)
; X32-SSE1-NEXT: movw %cx, 14(%eax) ; X32-SSE1-NEXT: movw %cx, 14(%eax)
; X32-SSE1-NEXT: movl %esi, 6(%eax) ; X32-SSE1-NEXT: movl %esi, 6(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi37:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi38:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_8i16_i16_23u567u9: ; X32-SSE41-LABEL: merge_8i16_i16_23u567u9:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movups 4(%eax), %xmm0 ; X32-SSE41-NEXT: movups 4(%eax), %xmm0
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
%ptr0 = getelementptr inbounds i16, i16* %ptr, i64 2 %ptr0 = getelementptr inbounds i16, i16* %ptr, i64 2
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; AVX-LABEL: merge_16i8_i8_01u3456789ABCDuF: ; AVX-LABEL: merge_16i8_i8_01u3456789ABCDuF:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovups (%rdi), %xmm0 ; AVX-NEXT: vmovups (%rdi), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF: ; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %ebp ; X32-SSE1-NEXT: pushl %ebp
; X32-SSE1-NEXT: .Lcfi26: ; X32-SSE1-NEXT: .Lcfi39:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %ebx ; X32-SSE1-NEXT: pushl %ebx
; X32-SSE1-NEXT: .Lcfi27: ; X32-SSE1-NEXT: .Lcfi40:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi28: ; X32-SSE1-NEXT: .Lcfi41:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 16 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 16
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi29: ; X32-SSE1-NEXT: .Lcfi42:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 20 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 20
; X32-SSE1-NEXT: .Lcfi30: ; X32-SSE1-NEXT: .Lcfi43:
; X32-SSE1-NEXT: .cfi_offset %esi, -20 ; X32-SSE1-NEXT: .cfi_offset %esi, -20
; X32-SSE1-NEXT: .Lcfi31: ; X32-SSE1-NEXT: .Lcfi44:
; X32-SSE1-NEXT: .cfi_offset %edi, -16 ; X32-SSE1-NEXT: .cfi_offset %edi, -16
; X32-SSE1-NEXT: .Lcfi32: ; X32-SSE1-NEXT: .Lcfi45:
; X32-SSE1-NEXT: .cfi_offset %ebx, -12 ; X32-SSE1-NEXT: .cfi_offset %ebx, -12
; X32-SSE1-NEXT: .Lcfi33: ; X32-SSE1-NEXT: .Lcfi46:
; X32-SSE1-NEXT: .cfi_offset %ebp, -8 ; X32-SSE1-NEXT: .cfi_offset %ebp, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movzwl (%ecx), %ebp ; X32-SSE1-NEXT: movzwl (%ecx), %ebp
; X32-SSE1-NEXT: movl 3(%ecx), %esi ; X32-SSE1-NEXT: movl 3(%ecx), %esi
; X32-SSE1-NEXT: movl 7(%ecx), %edi ; X32-SSE1-NEXT: movl 7(%ecx), %edi
; X32-SSE1-NEXT: movzwl 11(%ecx), %ebx ; X32-SSE1-NEXT: movzwl 11(%ecx), %ebx
; X32-SSE1-NEXT: movb 13(%ecx), %dl ; X32-SSE1-NEXT: movb 13(%ecx), %dl
; X32-SSE1-NEXT: movb 15(%ecx), %cl ; X32-SSE1-NEXT: movb 15(%ecx), %cl
; X32-SSE1-NEXT: movb %dl, 13(%eax) ; X32-SSE1-NEXT: movb %dl, 13(%eax)
; X32-SSE1-NEXT: movb %cl, 15(%eax) ; X32-SSE1-NEXT: movb %cl, 15(%eax)
; X32-SSE1-NEXT: movw %bx, 11(%eax) ; X32-SSE1-NEXT: movw %bx, 11(%eax)
; X32-SSE1-NEXT: movl %edi, 7(%eax) ; X32-SSE1-NEXT: movl %edi, 7(%eax)
; X32-SSE1-NEXT: movl %esi, 3(%eax) ; X32-SSE1-NEXT: movl %esi, 3(%eax)
; X32-SSE1-NEXT: movw %bp, (%eax) ; X32-SSE1-NEXT: movw %bp, (%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi47:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 16
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi48:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: popl %ebx ; X32-SSE1-NEXT: popl %ebx
; X32-SSE1-NEXT: .Lcfi49:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %ebp ; X32-SSE1-NEXT: popl %ebp
; X32-SSE1-NEXT: .Lcfi50:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_16i8_i8_01u3456789ABCDuF: ; X32-SSE41-LABEL: merge_16i8_i8_01u3456789ABCDuF:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movups (%eax), %xmm0 ; X32-SSE41-NEXT: movups (%eax), %xmm0
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
%ptr0 = getelementptr inbounds i8, i8* %ptr, i64 0 %ptr0 = getelementptr inbounds i8, i8* %ptr, i64 0
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_2i64_i64_12_volatile: ; X32-SSE1-LABEL: merge_2i64_i64_12_volatile:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi ; X32-SSE1-NEXT: pushl %edi
; X32-SSE1-NEXT: .Lcfi34: ; X32-SSE1-NEXT: .Lcfi51:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi ; X32-SSE1-NEXT: pushl %esi
; X32-SSE1-NEXT: .Lcfi35: ; X32-SSE1-NEXT: .Lcfi52:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12 ; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: .Lcfi36: ; X32-SSE1-NEXT: .Lcfi53:
; X32-SSE1-NEXT: .cfi_offset %esi, -12 ; X32-SSE1-NEXT: .cfi_offset %esi, -12
; X32-SSE1-NEXT: .Lcfi37: ; X32-SSE1-NEXT: .Lcfi54:
; X32-SSE1-NEXT: .cfi_offset %edi, -8 ; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE1-NEXT: movl 8(%ecx), %edx ; X32-SSE1-NEXT: movl 8(%ecx), %edx
; X32-SSE1-NEXT: movl 12(%ecx), %esi ; X32-SSE1-NEXT: movl 12(%ecx), %esi
; X32-SSE1-NEXT: movl 16(%ecx), %edi ; X32-SSE1-NEXT: movl 16(%ecx), %edi
; X32-SSE1-NEXT: movl 20(%ecx), %ecx ; X32-SSE1-NEXT: movl 20(%ecx), %ecx
; X32-SSE1-NEXT: movl %ecx, 12(%eax) ; X32-SSE1-NEXT: movl %ecx, 12(%eax)
; X32-SSE1-NEXT: movl %edi, 8(%eax) ; X32-SSE1-NEXT: movl %edi, 8(%eax)
; X32-SSE1-NEXT: movl %esi, 4(%eax) ; X32-SSE1-NEXT: movl %esi, 4(%eax)
; X32-SSE1-NEXT: movl %edx, (%eax) ; X32-SSE1-NEXT: movl %edx, (%eax)
; X32-SSE1-NEXT: popl %esi ; X32-SSE1-NEXT: popl %esi
; X32-SSE1-NEXT: .Lcfi55:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: popl %edi ; X32-SSE1-NEXT: popl %edi
; X32-SSE1-NEXT: .Lcfi56:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 4
; X32-SSE1-NEXT: retl $4 ; X32-SSE1-NEXT: retl $4
; ;
; X32-SSE41-LABEL: merge_2i64_i64_12_volatile: ; X32-SSE41-LABEL: merge_2i64_i64_12_volatile:
; X32-SSE41: # BB#0: ; X32-SSE41: # BB#0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-SSE41-NEXT: pinsrd $1, 12(%eax), %xmm0 ; X32-SSE41-NEXT: pinsrd $1, 12(%eax), %xmm0
; X32-SSE41-NEXT: pinsrd $2, 16(%eax), %xmm0 ; X32-SSE41-NEXT: pinsrd $2, 16(%eax), %xmm0
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