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Differential D35844 Diff 119589 test/CodeGen/X86/legalize-shift-64.ll

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test/CodeGen/X86/legalize-shift-64.ll

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; CHECK-NEXT: movl %ebx, %ebp ; CHECK-NEXT: movl %ebx, %ebp
; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: .LBB4_4: ; CHECK-NEXT: .LBB4_4:
; CHECK-NEXT: movl %ebp, 12(%eax) ; CHECK-NEXT: movl %ebp, 12(%eax)
; CHECK-NEXT: movl %ebx, 8(%eax) ; CHECK-NEXT: movl %ebx, 8(%eax)
; CHECK-NEXT: movl %esi, 4(%eax) ; CHECK-NEXT: movl %esi, 4(%eax)
; CHECK-NEXT: movl %edi, (%eax) ; CHECK-NEXT: movl %edi, (%eax)
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: .Lcfi8:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: .Lcfi9:
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebx
; CHECK-NEXT: .Lcfi10:
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .Lcfi11:
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl $4 ; CHECK-NEXT: retl $4
%shl = shl <2 x i64> %A, %B %shl = shl <2 x i64> %A, %B
ret <2 x i64> %shl ret <2 x i64> %shl
} }
; PR16108 ; PR16108
define i32 @test6() { define i32 @test6() {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .Lcfi8: ; CHECK-NEXT: .Lcfi12:
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi9: ; CHECK-NEXT: .Lcfi13:
; CHECK-NEXT: .cfi_offset %ebp, -8 ; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .Lcfi10: ; CHECK-NEXT: .Lcfi14:
; CHECK-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp ; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $16, %esp ; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: shldl $32, %eax, %ecx ; CHECK-NEXT: shldl $32, %eax, %ecx
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; CHECK-NEXT: # BB#3: # %if.then ; CHECK-NEXT: # BB#3: # %if.then
; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: jmp .LBB5_4 ; CHECK-NEXT: jmp .LBB5_4
; CHECK-NEXT: .LBB5_5: # %if.end ; CHECK-NEXT: .LBB5_5: # %if.end
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .LBB5_4: # %if.then ; CHECK-NEXT: .LBB5_4: # %if.then
; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .Lcfi15:
; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%x = alloca i32, align 4 %x = alloca i32, align 4
%t = alloca i64, align 8 %t = alloca i64, align 8
store volatile i32 1, i32* %x, align 4 store volatile i32 1, i32* %x, align 4
%load = load volatile i32, i32* %x, align 4 %load = load volatile i32, i32* %x, align 4
%shl = shl i32 %load, 8 %shl = shl i32 %load, 8
%add = add i32 %shl, -224 %add = add i32 %shl, -224
%sh_prom = zext i32 %add to i64 %sh_prom = zext i32 %add to i64
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