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Differential D35844 Diff 119589 test/CodeGen/X86/fast-isel-store.ll

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test/CodeGen/X86/fast-isel-store.ll

Show First 20 Lines • Show All 370 Lines • ▼ Show 20 Lines
; SSE64-NEXT: .Lcfi0: ; SSE64-NEXT: .Lcfi0:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd %xmm2, %xmm0 ; SSE64-NEXT: addpd %xmm2, %xmm0
; SSE64-NEXT: movupd %xmm0, (%eax) ; SSE64-NEXT: movupd %xmm0, (%eax)
; SSE64-NEXT: movupd %xmm1, 16(%eax) ; SSE64-NEXT: movupd %xmm1, 16(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi1:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVX32-LABEL: test_store_4xf64: ; AVX32-LABEL: test_store_4xf64:
; AVX32: # BB#0: ; AVX32: # BB#0:
; AVX32-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX32-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX32-NEXT: vmovupd %ymm0, (%rdi) ; AVX32-NEXT: vmovupd %ymm0, (%rdi)
; AVX32-NEXT: retq ; AVX32-NEXT: retq
; ;
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; SSE32-NEXT: addpd %xmm2, %xmm0 ; SSE32-NEXT: addpd %xmm2, %xmm0
; SSE32-NEXT: movapd %xmm0, (%rdi) ; SSE32-NEXT: movapd %xmm0, (%rdi)
; SSE32-NEXT: movapd %xmm1, 16(%rdi) ; SSE32-NEXT: movapd %xmm1, 16(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_4xf64_aligned: ; SSE64-LABEL: test_store_4xf64_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi1: ; SSE64-NEXT: .Lcfi2:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd %xmm2, %xmm0 ; SSE64-NEXT: addpd %xmm2, %xmm0
; SSE64-NEXT: movapd %xmm0, (%eax) ; SSE64-NEXT: movapd %xmm0, (%eax)
; SSE64-NEXT: movapd %xmm1, 16(%eax) ; SSE64-NEXT: movapd %xmm1, 16(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi3:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVX32-LABEL: test_store_4xf64_aligned: ; AVX32-LABEL: test_store_4xf64_aligned:
; AVX32: # BB#0: ; AVX32: # BB#0:
; AVX32-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX32-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX32-NEXT: vmovapd %ymm0, (%rdi) ; AVX32-NEXT: vmovapd %ymm0, (%rdi)
; AVX32-NEXT: retq ; AVX32-NEXT: retq
; ;
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; SSE32-NEXT: movups %xmm1, 16(%rdi) ; SSE32-NEXT: movups %xmm1, 16(%rdi)
; SSE32-NEXT: movups %xmm2, 32(%rdi) ; SSE32-NEXT: movups %xmm2, 32(%rdi)
; SSE32-NEXT: movups %xmm3, 48(%rdi) ; SSE32-NEXT: movups %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xi32: ; SSE64-LABEL: test_store_16xi32:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi2: ; SSE64-NEXT: .Lcfi4:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movups %xmm0, (%eax) ; SSE64-NEXT: movups %xmm0, (%eax)
; SSE64-NEXT: movups %xmm1, 16(%eax) ; SSE64-NEXT: movups %xmm1, 16(%eax)
; SSE64-NEXT: movups %xmm2, 32(%eax) ; SSE64-NEXT: movups %xmm2, 32(%eax)
; SSE64-NEXT: movups %xmm3, 48(%eax) ; SSE64-NEXT: movups %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi5:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVXONLY32-LABEL: test_store_16xi32: ; AVXONLY32-LABEL: test_store_16xi32:
; AVXONLY32: # BB#0: ; AVXONLY32: # BB#0:
; AVXONLY32-NEXT: vmovups %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovups %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovups %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovups %ymm1, 32(%rdi)
; AVXONLY32-NEXT: retq ; AVXONLY32-NEXT: retq
; ;
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; SSE32-NEXT: movaps %xmm1, 16(%rdi) ; SSE32-NEXT: movaps %xmm1, 16(%rdi)
; SSE32-NEXT: movaps %xmm2, 32(%rdi) ; SSE32-NEXT: movaps %xmm2, 32(%rdi)
; SSE32-NEXT: movaps %xmm3, 48(%rdi) ; SSE32-NEXT: movaps %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xi32_aligned: ; SSE64-LABEL: test_store_16xi32_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi3: ; SSE64-NEXT: .Lcfi6:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movaps %xmm0, (%eax) ; SSE64-NEXT: movaps %xmm0, (%eax)
; SSE64-NEXT: movaps %xmm1, 16(%eax) ; SSE64-NEXT: movaps %xmm1, 16(%eax)
; SSE64-NEXT: movaps %xmm2, 32(%eax) ; SSE64-NEXT: movaps %xmm2, 32(%eax)
; SSE64-NEXT: movaps %xmm3, 48(%eax) ; SSE64-NEXT: movaps %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi7:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVXONLY32-LABEL: test_store_16xi32_aligned: ; AVXONLY32-LABEL: test_store_16xi32_aligned:
; AVXONLY32: # BB#0: ; AVXONLY32: # BB#0:
; AVXONLY32-NEXT: vmovaps %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovaps %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovaps %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovaps %ymm1, 32(%rdi)
; AVXONLY32-NEXT: retq ; AVXONLY32-NEXT: retq
; ;
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; SSE32-NEXT: movups %xmm1, 16(%rdi) ; SSE32-NEXT: movups %xmm1, 16(%rdi)
; SSE32-NEXT: movups %xmm2, 32(%rdi) ; SSE32-NEXT: movups %xmm2, 32(%rdi)
; SSE32-NEXT: movups %xmm3, 48(%rdi) ; SSE32-NEXT: movups %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xf32: ; SSE64-LABEL: test_store_16xf32:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi4: ; SSE64-NEXT: .Lcfi8:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movups %xmm0, (%eax) ; SSE64-NEXT: movups %xmm0, (%eax)
; SSE64-NEXT: movups %xmm1, 16(%eax) ; SSE64-NEXT: movups %xmm1, 16(%eax)
; SSE64-NEXT: movups %xmm2, 32(%eax) ; SSE64-NEXT: movups %xmm2, 32(%eax)
; SSE64-NEXT: movups %xmm3, 48(%eax) ; SSE64-NEXT: movups %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi9:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVXONLY32-LABEL: test_store_16xf32: ; AVXONLY32-LABEL: test_store_16xf32:
; AVXONLY32: # BB#0: ; AVXONLY32: # BB#0:
; AVXONLY32-NEXT: vmovups %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovups %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovups %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovups %ymm1, 32(%rdi)
; AVXONLY32-NEXT: retq ; AVXONLY32-NEXT: retq
; ;
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; SSE32-NEXT: movaps %xmm1, 16(%rdi) ; SSE32-NEXT: movaps %xmm1, 16(%rdi)
; SSE32-NEXT: movaps %xmm2, 32(%rdi) ; SSE32-NEXT: movaps %xmm2, 32(%rdi)
; SSE32-NEXT: movaps %xmm3, 48(%rdi) ; SSE32-NEXT: movaps %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_16xf32_aligned: ; SSE64-LABEL: test_store_16xf32_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi5: ; SSE64-NEXT: .Lcfi10:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: movaps %xmm0, (%eax) ; SSE64-NEXT: movaps %xmm0, (%eax)
; SSE64-NEXT: movaps %xmm1, 16(%eax) ; SSE64-NEXT: movaps %xmm1, 16(%eax)
; SSE64-NEXT: movaps %xmm2, 32(%eax) ; SSE64-NEXT: movaps %xmm2, 32(%eax)
; SSE64-NEXT: movaps %xmm3, 48(%eax) ; SSE64-NEXT: movaps %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi11:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVXONLY32-LABEL: test_store_16xf32_aligned: ; AVXONLY32-LABEL: test_store_16xf32_aligned:
; AVXONLY32: # BB#0: ; AVXONLY32: # BB#0:
; AVXONLY32-NEXT: vmovaps %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovaps %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovaps %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovaps %ymm1, 32(%rdi)
; AVXONLY32-NEXT: retq ; AVXONLY32-NEXT: retq
; ;
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; SSE32-NEXT: movupd %xmm1, 16(%rdi) ; SSE32-NEXT: movupd %xmm1, 16(%rdi)
; SSE32-NEXT: movupd %xmm2, 32(%rdi) ; SSE32-NEXT: movupd %xmm2, 32(%rdi)
; SSE32-NEXT: movupd %xmm3, 48(%rdi) ; SSE32-NEXT: movupd %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_8xf64: ; SSE64-LABEL: test_store_8xf64:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi6: ; SSE64-NEXT: .Lcfi12:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0
; SSE64-NEXT: movupd %xmm0, (%eax) ; SSE64-NEXT: movupd %xmm0, (%eax)
; SSE64-NEXT: movupd %xmm1, 16(%eax) ; SSE64-NEXT: movupd %xmm1, 16(%eax)
; SSE64-NEXT: movupd %xmm2, 32(%eax) ; SSE64-NEXT: movupd %xmm2, 32(%eax)
; SSE64-NEXT: movupd %xmm3, 48(%eax) ; SSE64-NEXT: movupd %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi13:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVXONLY32-LABEL: test_store_8xf64: ; AVXONLY32-LABEL: test_store_8xf64:
; AVXONLY32: # BB#0: ; AVXONLY32: # BB#0:
; AVXONLY32-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVXONLY32-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY32-NEXT: vmovupd %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovupd %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovupd %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovupd %ymm1, 32(%rdi)
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; AVXONLY64-NEXT: subl $32, %esp ; AVXONLY64-NEXT: subl $32, %esp
; AVXONLY64-NEXT: movl 8(%ebp), %eax ; AVXONLY64-NEXT: movl 8(%ebp), %eax
; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1 ; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1
; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY64-NEXT: vmovupd %ymm0, (%eax) ; AVXONLY64-NEXT: vmovupd %ymm0, (%eax)
; AVXONLY64-NEXT: vmovupd %ymm1, 32(%eax) ; AVXONLY64-NEXT: vmovupd %ymm1, 32(%eax)
; AVXONLY64-NEXT: movl %ebp, %esp ; AVXONLY64-NEXT: movl %ebp, %esp
; AVXONLY64-NEXT: popl %ebp ; AVXONLY64-NEXT: popl %ebp
; AVXONLY64-NEXT: .Lcfi3:
; AVXONLY64-NEXT: .cfi_def_cfa %esp, 4
; AVXONLY64-NEXT: retl ; AVXONLY64-NEXT: retl
; ;
; AVX51232-LABEL: test_store_8xf64: ; AVX51232-LABEL: test_store_8xf64:
; AVX51232: # BB#0: ; AVX51232: # BB#0:
; AVX51232-NEXT: vaddpd %zmm1, %zmm0, %zmm0 ; AVX51232-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; AVX51232-NEXT: vmovupd %zmm0, (%rdi) ; AVX51232-NEXT: vmovupd %zmm0, (%rdi)
; AVX51232-NEXT: retq ; AVX51232-NEXT: retq
; ;
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; SSE32-NEXT: movapd %xmm1, 16(%rdi) ; SSE32-NEXT: movapd %xmm1, 16(%rdi)
; SSE32-NEXT: movapd %xmm2, 32(%rdi) ; SSE32-NEXT: movapd %xmm2, 32(%rdi)
; SSE32-NEXT: movapd %xmm3, 48(%rdi) ; SSE32-NEXT: movapd %xmm3, 48(%rdi)
; SSE32-NEXT: retq ; SSE32-NEXT: retq
; ;
; SSE64-LABEL: test_store_8xf64_aligned: ; SSE64-LABEL: test_store_8xf64_aligned:
; SSE64: # BB#0: ; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp ; SSE64-NEXT: subl $12, %esp
; SSE64-NEXT: .Lcfi7: ; SSE64-NEXT: .Lcfi14:
; SSE64-NEXT: .cfi_def_cfa_offset 16 ; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm2
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0 ; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm0
; SSE64-NEXT: movapd %xmm0, (%eax) ; SSE64-NEXT: movapd %xmm0, (%eax)
; SSE64-NEXT: movapd %xmm1, 16(%eax) ; SSE64-NEXT: movapd %xmm1, 16(%eax)
; SSE64-NEXT: movapd %xmm2, 32(%eax) ; SSE64-NEXT: movapd %xmm2, 32(%eax)
; SSE64-NEXT: movapd %xmm3, 48(%eax) ; SSE64-NEXT: movapd %xmm3, 48(%eax)
; SSE64-NEXT: addl $12, %esp ; SSE64-NEXT: addl $12, %esp
; SSE64-NEXT: .Lcfi15:
; SSE64-NEXT: .cfi_def_cfa_offset 4
; SSE64-NEXT: retl ; SSE64-NEXT: retl
; ;
; AVXONLY32-LABEL: test_store_8xf64_aligned: ; AVXONLY32-LABEL: test_store_8xf64_aligned:
; AVXONLY32: # BB#0: ; AVXONLY32: # BB#0:
; AVXONLY32-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVXONLY32-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY32-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY32-NEXT: vmovapd %ymm0, (%rdi) ; AVXONLY32-NEXT: vmovapd %ymm0, (%rdi)
; AVXONLY32-NEXT: vmovapd %ymm1, 32(%rdi) ; AVXONLY32-NEXT: vmovapd %ymm1, 32(%rdi)
; AVXONLY32-NEXT: retq ; AVXONLY32-NEXT: retq
; ;
; AVXONLY64-LABEL: test_store_8xf64_aligned: ; AVXONLY64-LABEL: test_store_8xf64_aligned:
; AVXONLY64: # BB#0: ; AVXONLY64: # BB#0:
; AVXONLY64-NEXT: pushl %ebp ; AVXONLY64-NEXT: pushl %ebp
; AVXONLY64-NEXT: .Lcfi3:
; AVXONLY64-NEXT: .cfi_def_cfa_offset 8
; AVXONLY64-NEXT: .Lcfi4: ; AVXONLY64-NEXT: .Lcfi4:
; AVXONLY64-NEXT: .cfi_def_cfa_offset 8
; AVXONLY64-NEXT: .Lcfi5:
; AVXONLY64-NEXT: .cfi_offset %ebp, -8 ; AVXONLY64-NEXT: .cfi_offset %ebp, -8
; AVXONLY64-NEXT: movl %esp, %ebp ; AVXONLY64-NEXT: movl %esp, %ebp
; AVXONLY64-NEXT: .Lcfi5: ; AVXONLY64-NEXT: .Lcfi6:
; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp ; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp
; AVXONLY64-NEXT: andl $-32, %esp ; AVXONLY64-NEXT: andl $-32, %esp
; AVXONLY64-NEXT: subl $32, %esp ; AVXONLY64-NEXT: subl $32, %esp
; AVXONLY64-NEXT: movl 8(%ebp), %eax ; AVXONLY64-NEXT: movl 8(%ebp), %eax
; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1 ; AVXONLY64-NEXT: vaddpd 40(%ebp), %ymm1, %ymm1
; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVXONLY64-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVXONLY64-NEXT: vmovapd %ymm0, (%eax) ; AVXONLY64-NEXT: vmovapd %ymm0, (%eax)
; AVXONLY64-NEXT: vmovapd %ymm1, 32(%eax) ; AVXONLY64-NEXT: vmovapd %ymm1, 32(%eax)
; AVXONLY64-NEXT: movl %ebp, %esp ; AVXONLY64-NEXT: movl %ebp, %esp
; AVXONLY64-NEXT: popl %ebp ; AVXONLY64-NEXT: popl %ebp
; AVXONLY64-NEXT: .Lcfi7:
; AVXONLY64-NEXT: .cfi_def_cfa %esp, 4
; AVXONLY64-NEXT: retl ; AVXONLY64-NEXT: retl
; ;
; AVX51232-LABEL: test_store_8xf64_aligned: ; AVX51232-LABEL: test_store_8xf64_aligned:
; AVX51232: # BB#0: ; AVX51232: # BB#0:
; AVX51232-NEXT: vaddpd %zmm1, %zmm0, %zmm0 ; AVX51232-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; AVX51232-NEXT: vmovapd %zmm0, (%rdi) ; AVX51232-NEXT: vmovapd %zmm0, (%rdi)
; AVX51232-NEXT: retq ; AVX51232-NEXT: retq
; ;
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