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llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
| Show First 20 Lines • Show All 1,199 Lines • ▼ Show 20 Lines | def immZExt5To31 : SDNodeXForm<imm, [{ | ||||
| return getImm(N, 31 - N->getZExtValue()); | return getImm(N, 31 - N->getZExtValue()); | ||||
| }]>; | }]>; | ||||
| // True if (N + 1) fits in 16-bit field. | // True if (N + 1) fits in 16-bit field. | ||||
| def immSExt16Plus1 : PatLeaf<(imm), [{ | def immSExt16Plus1 : PatLeaf<(imm), [{ | ||||
| return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); | return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); | ||||
| }]>; | }]>; | ||||
| def immZExtRange2To64 : PatLeaf<(imm), [{ | |||||
| return isUInt<7>(N->getZExtValue()) && (N->getZExtValue() >= 2) && | |||||
| (N->getZExtValue() <= 64); | |||||
| }]>; | |||||
| // Mips Address Mode! SDNode frameindex could possibily be a match | // Mips Address Mode! SDNode frameindex could possibily be a match | ||||
| // since load and store instructions from stack used it. | // since load and store instructions from stack used it. | ||||
| def addr : | def addr : | ||||
| ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; | ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; | ||||
| def addrRegImm : | def addrRegImm : | ||||
| ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; | ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; | ||||
| ▲ Show 20 Lines • Show All 455 Lines • ▼ Show 20 Lines | class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, | ||||
| Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm, | Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm, | ||||
| SDPatternOperator Op = null_frag> : | SDPatternOperator Op = null_frag> : | ||||
| InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), | InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), | ||||
| !strconcat(opstr, " $rt, $rs, $pos, $size"), | !strconcat(opstr, " $rt, $rs, $pos, $size"), | ||||
| [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT, | [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT, | ||||
| FrmR, opstr>, ISA_MIPS32R2; | FrmR, opstr>, ISA_MIPS32R2; | ||||
| class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, | class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, | ||||
| Operand SizeOpnd, SDPatternOperator Op = null_frag>: | Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm, | ||||
| SDPatternOperator Op = null_frag>: | |||||
| InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src), | InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src), | ||||
| !strconcat(opstr, " $rt, $rs, $pos, $size"), | !strconcat(opstr, " $rt, $rs, $pos, $size"), | ||||
| [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], | [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size, RO:$src))], | ||||
| II_INS, FrmR, opstr>, ISA_MIPS32R2 { | II_INS, FrmR, opstr>, ISA_MIPS32R2 { | ||||
| let Constraints = "$src = $rt"; | let Constraints = "$src = $rt"; | ||||
| } | } | ||||
| // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). | // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). | ||||
| class Atomic2Ops<PatFrag Op, RegisterClass DRC> : | class Atomic2Ops<PatFrag Op, RegisterClass DRC> : | ||||
| PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), | PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), | ||||
| [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; | [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; | ||||
| ▲ Show 20 Lines • Show All 487 Lines • ▼ Show 20 Lines | let AdditionalPredicates = [NotInMicroMips] in { | ||||
| def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, | def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, | ||||
| 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; | 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; | ||||
| def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; | def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; | ||||
| // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction | // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction | ||||
| def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, | def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, | ||||
| immZExt5, immZExt5Plus1, MipsExt>, | immZExt5, immZExt5Plus1, MipsExt>, | ||||
| EXT_FM<0>; | EXT_FM<0>; | ||||
| def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5, | def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5, | ||||
| uimm5_inssize_plus1, MipsIns>, | uimm5_inssize_plus1, immZExt5, | ||||
| immZExt5Plus1, MipsIns>, | |||||
| EXT_FM<4>; | EXT_FM<4>; | ||||
| } | } | ||||
| /// Move Control Registers From/To CPU Registers | /// Move Control Registers From/To CPU Registers | ||||
| let AdditionalPredicates = [NotInMicroMips] in { | let AdditionalPredicates = [NotInMicroMips] in { | ||||
| def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>, MFC3OP_FM<0x10, 4>, | def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>, MFC3OP_FM<0x10, 4>, | ||||
| ISA_MIPS32; | ISA_MIPS32; | ||||
| def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>, MFC3OP_FM<0x10, 0>, | def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>, MFC3OP_FM<0x10, 0>, | ||||
| ISA_MIPS32; | ISA_MIPS32; | ||||
| ▲ Show 20 Lines • Show All 764 Lines • Show Last 20 Lines | |||||