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Differential D34809 Diff 115196 llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

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llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines case Mips::DSRA_MM64R6:
Inst.setOpcode(Mips::DSRA32_MM64R6); Inst.setOpcode(Mips::DSRA32_MM64R6);
return; return;
case Mips::DROTR_MM64R6: case Mips::DROTR_MM64R6:
Inst.setOpcode(Mips::DROTR32_MM64R6); Inst.setOpcode(Mips::DROTR32_MM64R6);
return; return;
} }
} }
// Pick a DINS instruction variant based on the pos and size operands
static void LowerDins(MCInst& InstIn) {
assert(InstIn.getNumOperands() == 5 &&
"Invalid no. of machine operands for DINS!");
assert(InstIn.getOperand(2).isImm());
int64_t pos = InstIn.getOperand(2).getImm();
assert(InstIn.getOperand(3).isImm());
int64_t size = InstIn.getOperand(3).getImm();
assert((pos + size) <= 64 &&
"DINS cannot have position plus size over 64");
if (pos < 32) {
if ((pos + size) > 0 && (pos + size) <= 32)
return; // DINS, do nothing
else if ((pos + size) > 32) {
//DINSM
InstIn.getOperand(3).setImm(size - 32);
InstIn.setOpcode(Mips::DINSM);
}
} else if ((pos + size) > 32 && (pos + size) <= 64) {
// DINSU
InstIn.getOperand(2).setImm(pos - 32);
InstIn.setOpcode(Mips::DINSU);
}
}
// Fix a bad compact branch encoding for beqc/bnec. // Fix a bad compact branch encoding for beqc/bnec.
void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const { void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
// Encoding may be illegal !(rs < rt), but this situation is // Encoding may be illegal !(rs < rt), but this situation is
// easily fixed. // easily fixed.
unsigned RegOp0 = Inst.getOperand(0).getReg(); unsigned RegOp0 = Inst.getOperand(0).getReg();
unsigned RegOp1 = Inst.getOperand(1).getReg(); unsigned RegOp1 = Inst.getOperand(1).getReg();
unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 LinesencodeInstruction(const MCInst &MI, raw_ostream &OS,
case Mips::DSRA: case Mips::DSRA:
case Mips::DROTR: case Mips::DROTR:
case Mips::DSLL_MM64R6: case Mips::DSLL_MM64R6:
case Mips::DSRL_MM64R6: case Mips::DSRL_MM64R6:
case Mips::DSRA_MM64R6: case Mips::DSRA_MM64R6:
case Mips::DROTR_MM64R6: case Mips::DROTR_MM64R6:
LowerLargeShift(TmpInst); LowerLargeShift(TmpInst);
break; break;
// Double extract instruction is chosen by pos and size operands
case Mips::DINS:
LowerDins(TmpInst);
break;
// Compact branches, enforce encoding restrictions. // Compact branches, enforce encoding restrictions.
case Mips::BEQC: case Mips::BEQC:
case Mips::BNEC: case Mips::BNEC:
case Mips::BEQC64: case Mips::BEQC64:
case Mips::BNEC64: case Mips::BNEC64:
case Mips::BOVC: case Mips::BOVC:
case Mips::BOVC_MMR6: case Mips::BOVC_MMR6:
case Mips::BNVC: case Mips::BNVC:
▲ Show 20 Lines • Show All 935 Lines • Show Last 20 Lines