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llvm/trunk/lib/Target/X86/X86InstrInfo.td
Show First 20 Lines • Show All 265 Lines • ▼ Show 20 Lines | def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, | ||||
SDNPMemOperand]>; | SDNPMemOperand]>; | ||||
def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, | def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, | ||||
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, | [SDNPHasChain, SDNPMayStore, SDNPMayLoad, | ||||
SDNPMemOperand]>; | SDNPMemOperand]>; | ||||
def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, | def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, | ||||
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, | [SDNPHasChain, SDNPMayStore, SDNPMayLoad, | ||||
SDNPMemOperand]>; | SDNPMemOperand]>; | ||||
def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; | |||||
def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; | ||||
def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, | def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, | ||||
[SDNPHasChain, SDNPOutGlue]>; | [SDNPHasChain, SDNPOutGlue]>; | ||||
def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, | def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, | ||||
[SDNPHasChain]>; | [SDNPHasChain]>; | ||||
▲ Show 20 Lines • Show All 2,150 Lines • ▼ Show 20 Lines | def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), | ||||
(BZHI64rr GR64:$src, | (BZHI64rr GR64:$src, | ||||
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; | (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; | ||||
def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), | def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), | ||||
(i8 (trunc (sub 64, GR32:$lz)))), | (i8 (trunc (sub 64, GR32:$lz)))), | ||||
(BZHI64rm addr:$src, | (BZHI64rm addr:$src, | ||||
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; | (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; | ||||
} // HasBMI2 | } // HasBMI2 | ||||
let Predicates = [HasBMI] in { | |||||
def : Pat<(X86bextr GR32:$src1, GR32:$src2), | |||||
(BEXTR32rr GR32:$src1, GR32:$src2)>; | |||||
def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2), | |||||
(BEXTR32rm addr:$src1, GR32:$src2)>; | |||||
def : Pat<(X86bextr GR64:$src1, GR64:$src2), | |||||
(BEXTR64rr GR64:$src1, GR64:$src2)>; | |||||
def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2), | |||||
(BEXTR64rm addr:$src1, GR64:$src2)>; | |||||
} // HasBMI | |||||
multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, | multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, | ||||
X86MemOperand x86memop, Intrinsic Int, | X86MemOperand x86memop, Intrinsic Int, | ||||
PatFrag ld_frag> { | PatFrag ld_frag> { | ||||
def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), | def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), | ||||
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), | !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), | ||||
[(set RC:$dst, (Int RC:$src1, RC:$src2))]>, | [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, | ||||
VEX_4V; | VEX_4V; | ||||
def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), | def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), | ||||
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines | |||||
def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; | def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; | ||||
def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; | def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; | ||||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
// Pattern fragments to auto generate TBM instructions. | // Pattern fragments to auto generate TBM instructions. | ||||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
let Predicates = [HasTBM] in { | let Predicates = [HasTBM] in { | ||||
def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), | |||||
(BEXTRI32ri GR32:$src1, imm:$src2)>; | |||||
def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), | |||||
(BEXTRI32mi addr:$src1, imm:$src2)>; | |||||
def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2), | |||||
(BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>; | |||||
def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2), | |||||
(BEXTRI64mi addr:$src1, i64immSExt32:$src2)>; | |||||
// FIXME: patterns for the load versions are not implemented | // FIXME: patterns for the load versions are not implemented | ||||
def : Pat<(and GR32:$src, (add GR32:$src, 1)), | def : Pat<(and GR32:$src, (add GR32:$src, 1)), | ||||
(BLCFILL32rr GR32:$src)>; | (BLCFILL32rr GR32:$src)>; | ||||
def : Pat<(and GR64:$src, (add GR64:$src, 1)), | def : Pat<(and GR64:$src, (add GR64:$src, 1)), | ||||
(BLCFILL64rr GR64:$src)>; | (BLCFILL64rr GR64:$src)>; | ||||
def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), | def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), | ||||
(BLCI32rr GR32:$src)>; | (BLCI32rr GR32:$src)>; | ||||
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