Changeset View
Changeset View
Standalone View
Standalone View
lib/Target/RISCV/RISCVInstrInfo.td
| //===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===// | //===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===// | ||||
| // | // | ||||
| // The LLVM Compiler Infrastructure | // The LLVM Compiler Infrastructure | ||||
| // | // | ||||
| // This file is distributed under the University of Illinois Open Source | // This file is distributed under the University of Illinois Open Source | ||||
| // License. See LICENSE.TXT for details. | // License. See LICENSE.TXT for details. | ||||
| // | // | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // | // | ||||
| // This file describes the RISC-V instructions in TableGen format. | // This file describes the RISC-V instructions in TableGen format. | ||||
| // | // | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| include "RISCVInstrFormats.td" | include "RISCVInstrFormats.td" | ||||
| def SDT_RISCVCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, | |||||
| SDTCisVT<1, i32>]>; | |||||
| def SDT_RISCVCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, | |||||
| SDTCisVT<1, i32>]>; | |||||
| def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; | |||||
| def Call : SDNode<"RISCVISD::CALL", SDT_RISCVCall, | |||||
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, | |||||
| SDNPVariadic]>; | |||||
| def RetFlag : SDNode<"RISCVISD::RET_FLAG", SDTNone, | def RetFlag : SDNode<"RISCVISD::RET_FLAG", SDTNone, | ||||
| [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; | [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; | ||||
| def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_RISCVCallSeqStart, | |||||
| [SDNPHasChain, SDNPOutGlue]>; | |||||
| def CallSeqEnd : SDNode<"ISD::CALLSEQ_END", SDT_RISCVCallSeqEnd, | |||||
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; | |||||
| // Operands | // Operands | ||||
| class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass { | class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass { | ||||
| let Name = prefix # "Imm" # width # suffix; | let Name = prefix # "Imm" # width # suffix; | ||||
| let RenderMethod = "addImmOperands"; | let RenderMethod = "addImmOperands"; | ||||
| let DiagnosticType = !strconcat("Invalid", Name); | let DiagnosticType = !strconcat("Invalid", Name); | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines | |||||
| let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { | let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { | ||||
| def LUI : FU<0b0110111, (outs GPR:$rd), (ins uimm20:$imm20), | def LUI : FU<0b0110111, (outs GPR:$rd), (ins uimm20:$imm20), | ||||
| "lui\t$rd, $imm20", []>; | "lui\t$rd, $imm20", []>; | ||||
| def AUIPC : FU<0b0010111, (outs GPR:$rd), (ins uimm20:$imm20), | def AUIPC : FU<0b0010111, (outs GPR:$rd), (ins uimm20:$imm20), | ||||
| "auipc\t$rd, $imm20", []>; | "auipc\t$rd, $imm20", []>; | ||||
| let isCall = 1 in | |||||
| def JAL : FUJ<0b1101111, (outs GPR:$rd), (ins simm21_lsb0:$imm20), | def JAL : FUJ<0b1101111, (outs GPR:$rd), (ins simm21_lsb0:$imm20), | ||||
| "jal\t$rd, $imm20", []>; | "jal\t$rd, $imm20", []>; | ||||
| let isCall = 1 in | |||||
| def JALR : FI<0b000, 0b1100111, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), | def JALR : FI<0b000, 0b1100111, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), | ||||
| "jalr\t$rd, $rs1, $imm12", []>; | "jalr\t$rd, $rs1, $imm12", []>; | ||||
| } | } | ||||
| let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in | let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in | ||||
| class Bcc<bits<3> funct3, string OpcodeStr> : | class Bcc<bits<3> funct3, string OpcodeStr> : | ||||
| FSB<funct3, 0b1100011, (outs), (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), | FSB<funct3, 0b1100011, (outs), (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), | ||||
| OpcodeStr#"\t$rs1, $rs2, $imm12", []> { | OpcodeStr#"\t$rs1, $rs2, $imm12", []> { | ||||
| ▲ Show 20 Lines • Show All 189 Lines • ▼ Show 20 Lines | |||||
| // An extra pattern is needed for a brcond without a setcc (i.e. where the | // An extra pattern is needed for a brcond without a setcc (i.e. where the | ||||
| // condition was calculated elsewhere). | // condition was calculated elsewhere). | ||||
| def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0_32, bb:$imm12)>; | def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0_32, bb:$imm12)>; | ||||
| let isBarrier = 1, isTerminator = 1 in | let isBarrier = 1, isTerminator = 1 in | ||||
| def PseudoBR : Pseudo<(outs), (ins simm21_lsb0:$imm20), [(br bb:$imm20)]>, | def PseudoBR : Pseudo<(outs), (ins simm21_lsb0:$imm20), [(br bb:$imm20)]>, | ||||
| PseudoInstExpansion<(JAL X0_32, simm21_lsb0:$imm20)>; | PseudoInstExpansion<(JAL X0_32, simm21_lsb0:$imm20)>; | ||||
| let isCall = 1, Defs=[X1_32] in | |||||
kparzysz: Please add spaces between Defs and []. | |||||
| def PseudoCALL : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>, | |||||
| PseudoInstExpansion<(JALR X1_32, GPR:$rs1, 0)>; | |||||
| let isBarrier = 1, isReturn = 1, isTerminator = 1 in | let isBarrier = 1, isReturn = 1, isTerminator = 1 in | ||||
| def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>, | def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>, | ||||
| PseudoInstExpansion<(JALR X0_32, X1_32, 0)>; | PseudoInstExpansion<(JALR X0_32, X1_32, 0)>; | ||||
| /// Loads | /// Loads | ||||
| multiclass LdPat<PatFrag LoadOp, RISCVInst Inst> { | multiclass LdPat<PatFrag LoadOp, RISCVInst Inst> { | ||||
| def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>; | def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>; | ||||
| Show All 13 Lines | |||||
| multiclass StPat<PatFrag StoreOp, RISCVInst Inst> { | multiclass StPat<PatFrag StoreOp, RISCVInst Inst> { | ||||
| def : Pat<(StoreOp GPR:$rs2, GPR:$rs1), (Inst GPR:$rs2, GPR:$rs1, 0)>; | def : Pat<(StoreOp GPR:$rs2, GPR:$rs1), (Inst GPR:$rs2, GPR:$rs1, 0)>; | ||||
| def : Pat<(StoreOp GPR:$rs2, (add GPR:$rs1, simm12:$imm12)), (Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>; | def : Pat<(StoreOp GPR:$rs2, (add GPR:$rs1, simm12:$imm12)), (Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>; | ||||
| } | } | ||||
| defm : StPat<truncstorei8, SB>; | defm : StPat<truncstorei8, SB>; | ||||
| defm : StPat<truncstorei16, SH>; | defm : StPat<truncstorei16, SH>; | ||||
| defm : StPat<store, SW>; | defm : StPat<store, SW>; | ||||
| /// Other pseudo-instructions | |||||
| // Pessimistically assume the stack pointer will be clobbered | |||||
| let Defs = [X2_32], Uses = [X2_32] in { | |||||
| def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), | |||||
| [(CallSeqStart timm:$amt1, timm:$amt2)]>; | |||||
| def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), | |||||
| [(CallSeqEnd timm:$amt1, timm:$amt2)]>; | |||||
| } | |||||
Please add spaces between Defs and [].