Differential D29936 Diff 112750 lib/Target/RISCV/RISCVInstrInfo.cpp

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	#include "llvm/Support/ErrorHandling.h"			#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/TargetRegistry.h"			#include "llvm/Support/TargetRegistry.h"

	#define GET_INSTRINFO_CTOR_DTOR			#define GET_INSTRINFO_CTOR_DTOR
	#include "RISCVGenInstrInfo.inc"			#include "RISCVGenInstrInfo.inc"

	using namespace llvm;			using namespace llvm;

	RISCVInstrInfo::RISCVInstrInfo() : RISCVGenInstrInfo() {}			RISCVInstrInfo::RISCVInstrInfo()
				: RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {}
				apazosUnsubmitted Done Reply Inline Actions Code width standard is 80 columns. apazos: Code width standard is 80 columns.

	void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,			void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
	MachineBasicBlock::iterator Position,			MachineBasicBlock::iterator Position,
	const DebugLoc &DL,			const DebugLoc &DL,
	unsigned DestinationRegister,			unsigned DestinationRegister,
	unsigned SourceRegister,			unsigned SourceRegister,
	bool KillSource) const {			bool KillSource) const {
	if (!RISCV::GPRRegClass.contains(DestinationRegister, SourceRegister)) {			if (!RISCV::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
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