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Differential D36617 Diff 111898 test/CodeGen/X86/sse2-schedule.ll

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test/CodeGen/X86/sse2-schedule.ll

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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_addpd: ; ZNVER1-LABEL: test_addpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fadd <2 x double> %a0, %a1 %1 = fadd <2 x double> %a0, %a1
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = fadd <2 x double> %1, %2 %3 = fadd <2 x double> %1, %2
ret <2 x double> %3 ret <2 x double> %3
} }
define double @test_addsd(double %a0, double %a1, double *%a2) { define double @test_addsd(double %a0, double %a1, double *%a2) {
; GENERIC-LABEL: test_addsd: ; GENERIC-LABEL: test_addsd:
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; BTVER2-LABEL: test_addsd: ; BTVER2-LABEL: test_addsd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_addsd: ; ZNVER1-LABEL: test_addsd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fadd double %a0, %a1 %1 = fadd double %a0, %a1
%2 = load double, double *%a2, align 8 %2 = load double, double *%a2, align 8
%3 = fadd double %1, %2 %3 = fadd double %1, %2
ret double %3 ret double %3
} }
define <2 x double> @test_andpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_andpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_andpd: ; GENERIC-LABEL: test_andpd:
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_andpd: ; ZNVER1-LABEL: test_andpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = bitcast <2 x double> %a0 to <4 x i32> %1 = bitcast <2 x double> %a0 to <4 x i32>
%2 = bitcast <2 x double> %a1 to <4 x i32> %2 = bitcast <2 x double> %a1 to <4 x i32>
%3 = and <4 x i32> %1, %2 %3 = and <4 x i32> %1, %2
%4 = load <2 x double>, <2 x double> *%a2, align 16 %4 = load <2 x double>, <2 x double> *%a2, align 16
%5 = bitcast <2 x double> %4 to <4 x i32> %5 = bitcast <2 x double> %4 to <4 x i32>
%6 = and <4 x i32> %3, %5 %6 = and <4 x i32> %3, %5
%7 = bitcast <4 x i32> %6 to <2 x double> %7 = bitcast <4 x i32> %6 to <2 x double>
%8 = fadd <2 x double> %a1, %7 %8 = fadd <2 x double> %a1, %7
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; BTVER2-LABEL: test_andnotpd: ; BTVER2-LABEL: test_andnotpd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_andnotpd: ; ZNVER1-LABEL: test_andnotpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = bitcast <2 x double> %a0 to <4 x i32> %1 = bitcast <2 x double> %a0 to <4 x i32>
%2 = bitcast <2 x double> %a1 to <4 x i32> %2 = bitcast <2 x double> %a1 to <4 x i32>
%3 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1> %3 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
%4 = and <4 x i32> %3, %2 %4 = and <4 x i32> %3, %2
%5 = load <2 x double>, <2 x double> *%a2, align 16 %5 = load <2 x double>, <2 x double> *%a2, align 16
%6 = bitcast <2 x double> %5 to <4 x i32> %6 = bitcast <2 x double> %5 to <4 x i32>
%7 = xor <4 x i32> %4, <i32 -1, i32 -1, i32 -1, i32 -1> %7 = xor <4 x i32> %4, <i32 -1, i32 -1, i32 -1, i32 -1>
%8 = and <4 x i32> %6, %7 %8 = and <4 x i32> %6, %7
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; ;
; BTVER2-LABEL: test_cmppd: ; BTVER2-LABEL: test_cmppd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [3:1.00] ; BTVER2-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [3:1.00]
; BTVER2-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cmppd: ; ZNVER1-LABEL: test_cmppd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [3:1.00] ; ZNVER1-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [3:1.00]
; ZNVER1-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fcmp oeq <2 x double> %a0, %a1 %1 = fcmp oeq <2 x double> %a0, %a1
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = fcmp oeq <2 x double> %a0, %2 %3 = fcmp oeq <2 x double> %a0, %2
%4 = or <2 x i1> %1, %3 %4 = or <2 x i1> %1, %3
%5 = sext <2 x i1> %4 to <2 x i64> %5 = sext <2 x i1> %4 to <2 x i64>
%6 = bitcast <2 x i64> %5 to <2 x double> %6 = bitcast <2 x i64> %5 to <2 x double>
ret <2 x double> %6 ret <2 x double> %6
} }
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; HASWELL-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; HASWELL-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cmpsd: ; BTVER2-LABEL: test_cmpsd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cmpsd: ; ZNVER1-LABEL: test_cmpsd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = insertelement <2 x double> undef, double %a0, i32 0 %1 = insertelement <2 x double> undef, double %a0, i32 0
%2 = insertelement <2 x double> undef, double %a1, i32 0 %2 = insertelement <2 x double> undef, double %a1, i32 0
%3 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %1, <2 x double> %2, i8 0) %3 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %1, <2 x double> %2, i8 0)
%4 = load double, double *%a2, align 8 %4 = load double, double *%a2, align 8
%5 = insertelement <2 x double> undef, double %4, i32 0 %5 = insertelement <2 x double> undef, double %4, i32 0
%6 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %3, <2 x double> %5, i8 0) %6 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %3, <2 x double> %5, i8 0)
%7 = extractelement <2 x double> %6, i32 0 %7 = extractelement <2 x double> %6, i32 0
ret double %7 ret double %7
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; BTVER2-NEXT: movzbl %dl, %eax # sched: [1:0.50] ; BTVER2-NEXT: movzbl %dl, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_comisd: ; ZNVER1-LABEL: test_comisd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcomisd %xmm1, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vcomisd %xmm1, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: setnp %al # sched: [1:0.25] ; ZNVER1-NEXT: setnp %al # sched: [1:0.25]
; ZNVER1-NEXT: sete %cl # sched: [1:0.25] ; ZNVER1-NEXT: sete %cl # sched: [1:0.25]
; ZNVER1-NEXT: andb %al, %cl # sched: [1:0.25] ; ZNVER1-NEXT: andb %al, %cl # sched: [1:0.25]
; ZNVER1-NEXT: vcomisd (%rdi), %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vcomisd (%rdi), %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: setnp %al # sched: [1:0.25] ; ZNVER1-NEXT: setnp %al # sched: [1:0.25]
; ZNVER1-NEXT: sete %dl # sched: [1:0.25] ; ZNVER1-NEXT: sete %dl # sched: [1:0.25]
; ZNVER1-NEXT: andb %al, %dl # sched: [1:0.25] ; ZNVER1-NEXT: andb %al, %dl # sched: [1:0.25]
; ZNVER1-NEXT: orb %cl, %dl # sched: [1:0.25] ; ZNVER1-NEXT: orb %cl, %dl # sched: [1:0.25]
; ZNVER1-NEXT: movzbl %dl, %eax # sched: [1:0.25] ; ZNVER1-NEXT: movzbl %dl, %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) %1 = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1)
%2 = load <2 x double>, <2 x double> *%a2, align 8 %2 = load <2 x double>, <2 x double> *%a2, align 8
%3 = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %2) %3 = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %2)
%4 = or i32 %1, %3 %4 = or i32 %1, %3
ret i32 %4 ret i32 %4
} }
declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
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; HASWELL-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [8:1.00] ; HASWELL-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [8:1.00]
; HASWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtdq2pd: ; BTVER2-LABEL: test_cvtdq2pd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtdq2pd %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtdq2pd %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtdq2pd: ; ZNVER1-LABEL: test_cvtdq2pd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vcvtdq2pd %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtdq2pd %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <2 x i32> <i32 0, i32 1> %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
%2 = sitofp <2 x i32> %1 to <2 x double> %2 = sitofp <2 x i32> %1 to <2 x double>
%3 = load <4 x i32>, <4 x i32>*%a1, align 16 %3 = load <4 x i32>, <4 x i32>*%a1, align 16
%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <2 x i32> <i32 0, i32 1> %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
%5 = sitofp <2 x i32> %4 to <2 x double> %5 = sitofp <2 x i32> %4 to <2 x double>
%6 = fadd <2 x double> %2, %5 %6 = fadd <2 x double> %2, %5
ret <2 x double> %6 ret <2 x double> %6
} }
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; HASWELL-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [4:1.00] ; HASWELL-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [8:1.00] ; HASWELL-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [8:1.00]
; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtdq2ps: ; BTVER2-LABEL: test_cvtdq2ps:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtdq2ps: ; ZNVER1-LABEL: test_cvtdq2ps:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = sitofp <4 x i32> %a0 to <4 x float> %1 = sitofp <4 x i32> %a0 to <4 x float>
%2 = load <4 x i32>, <4 x i32>*%a1, align 16 %2 = load <4 x i32>, <4 x i32>*%a1, align 16
%3 = sitofp <4 x i32> %2 to <4 x float> %3 = sitofp <4 x i32> %2 to <4 x float>
%4 = fadd <4 x float> %1, %3 %4 = fadd <4 x float> %1, %3
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x i32> @test_cvtpd2dq(<2 x double> %a0, <2 x double> *%a1) { define <4 x i32> @test_cvtpd2dq(<2 x double> %a0, <2 x double> *%a1) {
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; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [4:1.00] ; HASWELL-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00] ; HASWELL-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtpd2dq: ; BTVER2-LABEL: test_cvtpd2dq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtpd2dq: ; ZNVER1-LABEL: test_cvtpd2dq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) %1 = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)
%2 = load <2 x double>, <2 x double> *%a1, align 16 %2 = load <2 x double>, <2 x double> *%a1, align 16
%3 = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %2) %3 = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %2)
%4 = add <4 x i32> %1, %3 %4 = add <4 x i32> %1, %3
ret <4 x i32> %4 ret <4 x i32> %4
} }
declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone
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; SANDY-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtpd2ps: ; HASWELL-LABEL: test_cvtpd2ps:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [4:1.00] ; HASWELL-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00] ; HASWELL-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00]
; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtpd2ps: ; BTVER2-LABEL: test_cvtpd2ps:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtpd2ps: ; ZNVER1-LABEL: test_cvtpd2ps:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [11:1.00]
; ZNVER1-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) %1 = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0)
%2 = load <2 x double>, <2 x double> *%a1, align 16 %2 = load <2 x double>, <2 x double> *%a1, align 16
%3 = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %2) %3 = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %2)
%4 = fadd <4 x float> %1, %3 %4 = fadd <4 x float> %1, %3
ret <4 x float> %4 ret <4 x float> %4
} }
declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone
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; ;
; HASWELL-LABEL: test_cvtps2dq: ; HASWELL-LABEL: test_cvtps2dq:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [7:1.00] ; HASWELL-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [7:1.00]
; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtps2dq: ; BTVER2-LABEL: test_cvtps2dq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtps2dq: ; ZNVER1-LABEL: test_cvtps2dq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) %1 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0)
%2 = load <4 x float>, <4 x float> *%a1, align 16 %2 = load <4 x float>, <4 x float> *%a1, align 16
%3 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %2) %3 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %2)
%4 = add <4 x i32> %1, %3 %4 = add <4 x i32> %1, %3
ret <4 x i32> %4 ret <4 x i32> %4
} }
declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone
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; SANDY-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [2:1.00] ; SANDY-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [2:1.00]
; SANDY-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [7:1.00] ; SANDY-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [7:1.00]
; SANDY-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtps2pd: ; HASWELL-LABEL: test_cvtps2pd:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [2:1.00] ; HASWELL-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [2:1.00]
; HASWELL-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [5:1.00] ; HASWELL-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [5:1.00]
; HASWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtps2pd: ; BTVER2-LABEL: test_cvtps2pd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtps2pd: ; ZNVER1-LABEL: test_cvtps2pd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [10:1.00]
; ZNVER1-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <4 x float> %a0, <4 x float> undef, <2 x i32> <i32 0, i32 1> %1 = shufflevector <4 x float> %a0, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%2 = fpext <2 x float> %1 to <2 x double> %2 = fpext <2 x float> %1 to <2 x double>
%3 = load <4 x float>, <4 x float> *%a1, align 16 %3 = load <4 x float>, <4 x float> *%a1, align 16
%4 = shufflevector <4 x float> %3, <4 x float> undef, <2 x i32> <i32 0, i32 1> %4 = shufflevector <4 x float> %3, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%5 = fpext <2 x float> %4 to <2 x double> %5 = fpext <2 x float> %4 to <2 x double>
%6 = fadd <2 x double> %2, %5 %6 = fadd <2 x double> %2, %5
ret <2 x double> %6 ret <2 x double> %6
} }
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; SANDY-NEXT: addl %ecx, %eax # sched: [1:0.33] ; SANDY-NEXT: addl %ecx, %eax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtsd2si: ; HASWELL-LABEL: test_cvtsd2si:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtsd2si %xmm0, %ecx # sched: [4:1.00] ; HASWELL-NEXT: vcvtsd2si %xmm0, %ecx # sched: [4:1.00]
; HASWELL-NEXT: vcvtsd2si (%rdi), %eax # sched: [8:1.00] ; HASWELL-NEXT: vcvtsd2si (%rdi), %eax # sched: [8:1.00]
; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25] ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtsd2si: ; BTVER2-LABEL: test_cvtsd2si:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtsd2si (%rdi), %eax # sched: [8:1.00] ; BTVER2-NEXT: vcvtsd2si (%rdi), %eax # sched: [8:1.00]
; BTVER2-NEXT: vcvtsd2si %xmm0, %ecx # sched: [3:1.00] ; BTVER2-NEXT: vcvtsd2si %xmm0, %ecx # sched: [3:1.00]
; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50] ; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtsd2si: ; ZNVER1-LABEL: test_cvtsd2si:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtsd2si (%rdi), %eax # sched: [12:1.00] ; ZNVER1-NEXT: vcvtsd2si (%rdi), %eax # sched: [12:1.00]
; ZNVER1-NEXT: vcvtsd2si %xmm0, %ecx # sched: [5:1.00] ; ZNVER1-NEXT: vcvtsd2si %xmm0, %ecx # sched: [5:1.00]
; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25] ; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = insertelement <2 x double> undef, double %a0, i32 0 %1 = insertelement <2 x double> undef, double %a0, i32 0
%2 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %1) %2 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %1)
%3 = load double, double *%a1, align 8 %3 = load double, double *%a1, align 8
%4 = insertelement <2 x double> undef, double %3, i32 0 %4 = insertelement <2 x double> undef, double %3, i32 0
%5 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %4) %5 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %4)
%6 = add i32 %2, %5 %6 = add i32 %2, %5
ret i32 %6 ret i32 %6
} }
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; SANDY-NEXT: vcvtsd2si (%rdi), %rax # sched: [10:1.00] ; SANDY-NEXT: vcvtsd2si (%rdi), %rax # sched: [10:1.00]
; SANDY-NEXT: addq %rcx, %rax # sched: [1:0.33] ; SANDY-NEXT: addq %rcx, %rax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtsd2siq: ; HASWELL-LABEL: test_cvtsd2siq:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtsd2si %xmm0, %rcx # sched: [4:1.00] ; HASWELL-NEXT: vcvtsd2si %xmm0, %rcx # sched: [4:1.00]
; HASWELL-NEXT: vcvtsd2si (%rdi), %rax # sched: [8:1.00] ; HASWELL-NEXT: vcvtsd2si (%rdi), %rax # sched: [8:1.00]
; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25] ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtsd2siq: ; BTVER2-LABEL: test_cvtsd2siq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtsd2si (%rdi), %rax # sched: [8:1.00] ; BTVER2-NEXT: vcvtsd2si (%rdi), %rax # sched: [8:1.00]
; BTVER2-NEXT: vcvtsd2si %xmm0, %rcx # sched: [3:1.00] ; BTVER2-NEXT: vcvtsd2si %xmm0, %rcx # sched: [3:1.00]
; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50] ; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtsd2siq: ; ZNVER1-LABEL: test_cvtsd2siq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtsd2si (%rdi), %rax # sched: [12:1.00] ; ZNVER1-NEXT: vcvtsd2si (%rdi), %rax # sched: [12:1.00]
; ZNVER1-NEXT: vcvtsd2si %xmm0, %rcx # sched: [5:1.00] ; ZNVER1-NEXT: vcvtsd2si %xmm0, %rcx # sched: [5:1.00]
; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25] ; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = insertelement <2 x double> undef, double %a0, i32 0 %1 = insertelement <2 x double> undef, double %a0, i32 0
%2 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %1) %2 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %1)
%3 = load double, double *%a1, align 8 %3 = load double, double *%a1, align 8
%4 = insertelement <2 x double> undef, double %3, i32 0 %4 = insertelement <2 x double> undef, double %3, i32 0
%5 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %4) %5 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %4)
%6 = add i64 %2, %5 %6 = add i64 %2, %5
ret i64 %6 ret i64 %6
} }
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; SANDY-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [6:0.50] ; SANDY-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [6:0.50]
; SANDY-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [4:1.00] ; SANDY-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
; SANDY-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtsd2ss: ; HASWELL-LABEL: test_cvtsd2ss:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [4:1.00] ; HASWELL-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [4:0.50] ; HASWELL-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [4:0.50]
; HASWELL-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [4:1.00] ; HASWELL-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
; HASWELL-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtsd2ss: ; BTVER2-LABEL: test_cvtsd2ss:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [5:1.00] ; BTVER2-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [5:1.00]
; BTVER2-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [3:1.00] ; BTVER2-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [3:1.00]
; BTVER2-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtsd2ss: ; ZNVER1-LABEL: test_cvtsd2ss:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [8:0.50] ; ZNVER1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [8:0.50]
; ZNVER1-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
; ZNVER1-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fptrunc double %a0 to float %1 = fptrunc double %a0 to float
%2 = load double, double *%a1, align 8 %2 = load double, double *%a1, align 8
%3 = fptrunc double %2 to float %3 = fptrunc double %2 to float
%4 = fadd float %1, %3 %4 = fadd float %1, %3
ret float %4 ret float %4
} }
define double @test_cvtsi2sd(i32 %a0, i32 *%a1) { define double @test_cvtsi2sd(i32 %a0, i32 *%a1) {
Show All 22 Lines
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00] ; SANDY-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00]
; SANDY-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00] ; SANDY-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; SANDY-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtsi2sd: ; HASWELL-LABEL: test_cvtsi2sd:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00] ; HASWELL-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00] ; HASWELL-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
; HASWELL-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtsi2sd: ; BTVER2-LABEL: test_cvtsi2sd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtsi2sd: ; ZNVER1-LABEL: test_cvtsi2sd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = sitofp i32 %a0 to double %1 = sitofp i32 %a0 to double
%2 = load i32, i32 *%a1, align 8 %2 = load i32, i32 *%a1, align 8
%3 = sitofp i32 %2 to double %3 = sitofp i32 %2 to double
%4 = fadd double %1, %3 %4 = fadd double %1, %3
ret double %4 ret double %4
} }
define double @test_cvtsi2sdq(i64 %a0, i64 *%a1) { define double @test_cvtsi2sdq(i64 %a0, i64 *%a1) {
Show All 21 Lines
; SANDY-LABEL: test_cvtsi2sdq: ; SANDY-LABEL: test_cvtsi2sdq:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00] ; SANDY-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00]
; SANDY-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00] ; SANDY-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; SANDY-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtsi2sdq: ; HASWELL-LABEL: test_cvtsi2sdq:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00] ; HASWELL-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00] ; HASWELL-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
; HASWELL-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtsi2sdq: ; BTVER2-LABEL: test_cvtsi2sdq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtsi2sdq: ; ZNVER1-LABEL: test_cvtsi2sdq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = sitofp i64 %a0 to double %1 = sitofp i64 %a0 to double
%2 = load i64, i64 *%a1, align 8 %2 = load i64, i64 *%a1, align 8
%3 = sitofp i64 %2 to double %3 = sitofp i64 %2 to double
%4 = fadd double %1, %3 %4 = fadd double %1, %3
ret double %4 ret double %4
} }
; TODO - cvtss2sd_m ; TODO - cvtss2sd_m
Show All 26 Lines
; ;
; SANDY-LABEL: test_cvtss2sd: ; SANDY-LABEL: test_cvtss2sd:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [1:1.00] ; SANDY-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [1:1.00]
; SANDY-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [6:0.50] ; SANDY-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [6:0.50]
; SANDY-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [1:1.00] ; SANDY-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [1:1.00]
; SANDY-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvtss2sd: ; HASWELL-LABEL: test_cvtss2sd:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [2:1.00] ; HASWELL-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [2:1.00]
; HASWELL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [4:0.50] ; HASWELL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [4:0.50]
; HASWELL-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [2:1.00] ; HASWELL-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [2:1.00]
; HASWELL-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvtss2sd: ; BTVER2-LABEL: test_cvtss2sd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:1.00] ; BTVER2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:1.00]
; BTVER2-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [3:1.00] ; BTVER2-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [3:1.00]
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvtss2sd: ; ZNVER1-LABEL: test_cvtss2sd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [8:0.50] ; ZNVER1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [8:0.50]
; ZNVER1-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [5:1.00] ; ZNVER1-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fpext float %a0 to double %1 = fpext float %a0 to double
%2 = load float, float *%a1, align 4 %2 = load float, float *%a1, align 4
%3 = fpext float %2 to double %3 = fpext float %2 to double
%4 = fadd double %1, %3 %4 = fadd double %1, %3
ret double %4 ret double %4
} }
define <4 x i32> @test_cvttpd2dq(<2 x double> %a0, <2 x double> *%a1) { define <4 x i32> @test_cvttpd2dq(<2 x double> %a0, <2 x double> *%a1) {
Show All 19 Lines
; SLM-NEXT: paddd %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: paddd %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_cvttpd2dq: ; SANDY-LABEL: test_cvttpd2dq:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [4:1.00] ; SANDY-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [4:1.00]
; SANDY-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [10:1.00] ; SANDY-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [10:1.00]
; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvttpd2dq: ; HASWELL-LABEL: test_cvttpd2dq:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [4:1.00] ; HASWELL-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [4:1.00]
; HASWELL-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00] ; HASWELL-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvttpd2dq: ; BTVER2-LABEL: test_cvttpd2dq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvttpd2dq: ; ZNVER1-LABEL: test_cvttpd2dq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fptosi <2 x double> %a0 to <2 x i32> %1 = fptosi <2 x double> %a0 to <2 x i32>
%2 = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = load <2 x double>, <2 x double> *%a1, align 16 %3 = load <2 x double>, <2 x double> *%a1, align 16
%4 = fptosi <2 x double> %3 to <2 x i32> %4 = fptosi <2 x double> %3 to <2 x i32>
%5 = shufflevector <2 x i32> %4, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %5 = shufflevector <2 x i32> %4, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%6 = add <4 x i32> %2, %5 %6 = add <4 x i32> %2, %5
ret <4 x i32> %6 ret <4 x i32> %6
} }
Show All 20 Lines
; SLM-NEXT: cvttps2dq (%rdi), %xmm0 # sched: [7:1.00] ; SLM-NEXT: cvttps2dq (%rdi), %xmm0 # sched: [7:1.00]
; SLM-NEXT: paddd %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: paddd %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_cvttps2dq: ; SANDY-LABEL: test_cvttps2dq:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [9:1.00] ; SANDY-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [9:1.00]
; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvttps2dq: ; HASWELL-LABEL: test_cvttps2dq:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00] ; HASWELL-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00]
; HASWELL-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [7:1.00] ; HASWELL-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [7:1.00]
; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvttps2dq: ; BTVER2-LABEL: test_cvttps2dq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [8:1.00] ; BTVER2-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [8:1.00]
; BTVER2-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvttps2dq: ; ZNVER1-LABEL: test_cvttps2dq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [12:1.00] ; ZNVER1-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [12:1.00]
; ZNVER1-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [5:1.00]
; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fptosi <4 x float> %a0 to <4 x i32> %1 = fptosi <4 x float> %a0 to <4 x i32>
%2 = load <4 x float>, <4 x float> *%a1, align 16 %2 = load <4 x float>, <4 x float> *%a1, align 16
%3 = fptosi <4 x float> %2 to <4 x i32> %3 = fptosi <4 x float> %2 to <4 x i32>
%4 = add <4 x i32> %1, %3 %4 = add <4 x i32> %1, %3
ret <4 x i32> %4 ret <4 x i32> %4
} }
define i32 @test_cvttsd2si(double %a0, double *%a1) { define i32 @test_cvttsd2si(double %a0, double *%a1) {
Show All 16 Lines
; SLM-NEXT: cvttsd2si (%rdi), %eax # sched: [7:1.00] ; SLM-NEXT: cvttsd2si (%rdi), %eax # sched: [7:1.00]
; SLM-NEXT: cvttsd2si %xmm0, %ecx # sched: [4:0.50] ; SLM-NEXT: cvttsd2si %xmm0, %ecx # sched: [4:0.50]
; SLM-NEXT: addl %ecx, %eax # sched: [1:0.50] ; SLM-NEXT: addl %ecx, %eax # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_cvttsd2si: ; SANDY-LABEL: test_cvttsd2si:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vcvttsd2si %xmm0, %ecx # sched: [5:1.00] ; SANDY-NEXT: vcvttsd2si %xmm0, %ecx # sched: [5:1.00]
; SANDY-NEXT: vcvttsd2si (%rdi), %eax # sched: [10:1.00] ; SANDY-NEXT: vcvttsd2si (%rdi), %eax # sched: [10:1.00]
; SANDY-NEXT: addl %ecx, %eax # sched: [1:0.33] ; SANDY-NEXT: addl %ecx, %eax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvttsd2si: ; HASWELL-LABEL: test_cvttsd2si:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvttsd2si %xmm0, %ecx # sched: [4:1.00] ; HASWELL-NEXT: vcvttsd2si %xmm0, %ecx # sched: [4:1.00]
; HASWELL-NEXT: vcvttsd2si (%rdi), %eax # sched: [8:1.00] ; HASWELL-NEXT: vcvttsd2si (%rdi), %eax # sched: [8:1.00]
; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25] ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvttsd2si: ; BTVER2-LABEL: test_cvttsd2si:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvttsd2si (%rdi), %eax # sched: [8:1.00] ; BTVER2-NEXT: vcvttsd2si (%rdi), %eax # sched: [8:1.00]
; BTVER2-NEXT: vcvttsd2si %xmm0, %ecx # sched: [3:1.00] ; BTVER2-NEXT: vcvttsd2si %xmm0, %ecx # sched: [3:1.00]
; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50] ; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvttsd2si: ; ZNVER1-LABEL: test_cvttsd2si:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvttsd2si (%rdi), %eax # sched: [12:1.00] ; ZNVER1-NEXT: vcvttsd2si (%rdi), %eax # sched: [12:1.00]
; ZNVER1-NEXT: vcvttsd2si %xmm0, %ecx # sched: [5:1.00] ; ZNVER1-NEXT: vcvttsd2si %xmm0, %ecx # sched: [5:1.00]
; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25] ; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fptosi double %a0 to i32 %1 = fptosi double %a0 to i32
%2 = load double, double *%a1, align 8 %2 = load double, double *%a1, align 8
%3 = fptosi double %2 to i32 %3 = fptosi double %2 to i32
%4 = add i32 %1, %3 %4 = add i32 %1, %3
ret i32 %4 ret i32 %4
} }
define i64 @test_cvttsd2siq(double %a0, double *%a1) { define i64 @test_cvttsd2siq(double %a0, double *%a1) {
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; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: cvttsd2si (%rdi), %rax # sched: [7:1.00] ; SLM-NEXT: cvttsd2si (%rdi), %rax # sched: [7:1.00]
; SLM-NEXT: cvttsd2si %xmm0, %rcx # sched: [4:0.50] ; SLM-NEXT: cvttsd2si %xmm0, %rcx # sched: [4:0.50]
; SLM-NEXT: addq %rcx, %rax # sched: [1:0.50] ; SLM-NEXT: addq %rcx, %rax # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_cvttsd2siq: ; SANDY-LABEL: test_cvttsd2siq:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vcvttsd2si %xmm0, %rcx # sched: [5:1.00] ; SANDY-NEXT: vcvttsd2si %xmm0, %rcx # sched: [5:1.00]
; SANDY-NEXT: vcvttsd2si (%rdi), %rax # sched: [10:1.00] ; SANDY-NEXT: vcvttsd2si (%rdi), %rax # sched: [10:1.00]
; SANDY-NEXT: addq %rcx, %rax # sched: [1:0.33] ; SANDY-NEXT: addq %rcx, %rax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_cvttsd2siq: ; HASWELL-LABEL: test_cvttsd2siq:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vcvttsd2si %xmm0, %rcx # sched: [4:1.00] ; HASWELL-NEXT: vcvttsd2si %xmm0, %rcx # sched: [4:1.00]
; HASWELL-NEXT: vcvttsd2si (%rdi), %rax # sched: [8:1.00] ; HASWELL-NEXT: vcvttsd2si (%rdi), %rax # sched: [8:1.00]
; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25] ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_cvttsd2siq: ; BTVER2-LABEL: test_cvttsd2siq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vcvttsd2si (%rdi), %rax # sched: [8:1.00] ; BTVER2-NEXT: vcvttsd2si (%rdi), %rax # sched: [8:1.00]
; BTVER2-NEXT: vcvttsd2si %xmm0, %rcx # sched: [3:1.00] ; BTVER2-NEXT: vcvttsd2si %xmm0, %rcx # sched: [3:1.00]
; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50] ; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_cvttsd2siq: ; ZNVER1-LABEL: test_cvttsd2siq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vcvttsd2si (%rdi), %rax # sched: [12:1.00] ; ZNVER1-NEXT: vcvttsd2si (%rdi), %rax # sched: [12:1.00]
; ZNVER1-NEXT: vcvttsd2si %xmm0, %rcx # sched: [5:1.00] ; ZNVER1-NEXT: vcvttsd2si %xmm0, %rcx # sched: [5:1.00]
; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25] ; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fptosi double %a0 to i64 %1 = fptosi double %a0 to i64
%2 = load double, double *%a1, align 8 %2 = load double, double *%a1, align 8
%3 = fptosi double %2 to i64 %3 = fptosi double %2 to i64
%4 = add i64 %1, %3 %4 = add i64 %1, %3
ret i64 %4 ret i64 %4
} }
define <2 x double> @test_divpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_divpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_divpd: ; GENERIC-LABEL: test_divpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: divpd %xmm1, %xmm0 # sched: [22:1.00] ; GENERIC-NEXT: divpd %xmm1, %xmm0 # sched: [22:1.00]
; GENERIC-NEXT: divpd (%rdi), %xmm0 # sched: [28:1.00] ; GENERIC-NEXT: divpd (%rdi), %xmm0 # sched: [28:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_divpd: ; ATOM-LABEL: test_divpd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: divpd %xmm1, %xmm0 # sched: [125:62.50] ; ATOM-NEXT: divpd %xmm1, %xmm0 # sched: [125:62.50]
; ATOM-NEXT: divpd (%rdi), %xmm0 # sched: [125:62.50] ; ATOM-NEXT: divpd (%rdi), %xmm0 # sched: [125:62.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_divpd: ; SLM-LABEL: test_divpd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: divpd %xmm1, %xmm0 # sched: [34:34.00] ; SLM-NEXT: divpd %xmm1, %xmm0 # sched: [34:34.00]
; SLM-NEXT: divpd (%rdi), %xmm0 # sched: [37:34.00] ; SLM-NEXT: divpd (%rdi), %xmm0 # sched: [37:34.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_divpd: ; SANDY-LABEL: test_divpd:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [22:1.00] ; SANDY-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [22:1.00]
; SANDY-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [28:1.00] ; SANDY-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [28:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_divpd: ; HASWELL-LABEL: test_divpd:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [12:1.00] ; HASWELL-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [12:1.00]
; HASWELL-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [16:1.00] ; HASWELL-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_divpd: ; BTVER2-LABEL: test_divpd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [19:19.00] ; BTVER2-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [19:19.00]
; BTVER2-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [24:19.00] ; BTVER2-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [24:19.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_divpd: ; ZNVER1-LABEL: test_divpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [15:1.00] ; ZNVER1-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [15:1.00]
; ZNVER1-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [22:1.00] ; ZNVER1-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [22:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fdiv <2 x double> %a0, %a1 %1 = fdiv <2 x double> %a0, %a1
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = fdiv <2 x double> %1, %2 %3 = fdiv <2 x double> %1, %2
ret <2 x double> %3 ret <2 x double> %3
} }
define double @test_divsd(double %a0, double %a1, double *%a2) { define double @test_divsd(double %a0, double %a1, double *%a2) {
; GENERIC-LABEL: test_divsd: ; GENERIC-LABEL: test_divsd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: divsd %xmm1, %xmm0 # sched: [22:1.00] ; GENERIC-NEXT: divsd %xmm1, %xmm0 # sched: [22:1.00]
; GENERIC-NEXT: divsd (%rdi), %xmm0 # sched: [28:1.00] ; GENERIC-NEXT: divsd (%rdi), %xmm0 # sched: [28:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_divsd: ; ATOM-LABEL: test_divsd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: divsd %xmm1, %xmm0 # sched: [62:31.00] ; ATOM-NEXT: divsd %xmm1, %xmm0 # sched: [62:31.00]
; ATOM-NEXT: divsd (%rdi), %xmm0 # sched: [62:31.00] ; ATOM-NEXT: divsd (%rdi), %xmm0 # sched: [62:31.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_divsd: ; SLM-LABEL: test_divsd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: divsd %xmm1, %xmm0 # sched: [34:34.00] ; SLM-NEXT: divsd %xmm1, %xmm0 # sched: [34:34.00]
; SLM-NEXT: divsd (%rdi), %xmm0 # sched: [37:34.00] ; SLM-NEXT: divsd (%rdi), %xmm0 # sched: [37:34.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_divsd: ; SANDY-LABEL: test_divsd:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [22:1.00] ; SANDY-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [22:1.00]
; SANDY-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [28:1.00] ; SANDY-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [28:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
Show All 9 Lines
; BTVER2-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [19:19.00] ; BTVER2-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [19:19.00]
; BTVER2-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [24:19.00] ; BTVER2-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [24:19.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_divsd: ; ZNVER1-LABEL: test_divsd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [15:1.00] ; ZNVER1-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [15:1.00]
; ZNVER1-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [22:1.00] ; ZNVER1-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [22:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fdiv double %a0, %a1 %1 = fdiv double %a0, %a1
%2 = load double, double *%a2, align 8 %2 = load double, double *%a2, align 8
%3 = fdiv double %1, %2 %3 = fdiv double %1, %2
ret double %3 ret double %3
} }
define void @test_lfence() { define void @test_lfence() {
; GENERIC-LABEL: test_lfence: ; GENERIC-LABEL: test_lfence:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: lfence # sched: [1:1.00] ; GENERIC-NEXT: lfence # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_lfence: ; ATOM-LABEL: test_lfence:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: lfence # sched: [1:0.50] ; ATOM-NEXT: lfence # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_lfence: ; SLM-LABEL: test_lfence:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: lfence # sched: [1:1.00] ; SLM-NEXT: lfence # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
Show All 10 Lines
; BTVER2-LABEL: test_lfence: ; BTVER2-LABEL: test_lfence:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: lfence # sched: [1:1.00] ; BTVER2-NEXT: lfence # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_lfence: ; ZNVER1-LABEL: test_lfence:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: lfence # sched: [1:0.50] ; ZNVER1-NEXT: lfence # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
call void @llvm.x86.sse2.lfence() call void @llvm.x86.sse2.lfence()
ret void ret void
} }
declare void @llvm.x86.sse2.lfence() nounwind readnone declare void @llvm.x86.sse2.lfence() nounwind readnone
define void @test_mfence() { define void @test_mfence() {
; GENERIC-LABEL: test_mfence: ; GENERIC-LABEL: test_mfence:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: mfence # sched: [1:1.00] ; GENERIC-NEXT: mfence # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_mfence: ; ATOM-LABEL: test_mfence:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: mfence # sched: [1:1.00] ; ATOM-NEXT: mfence # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_mfence: ; SLM-LABEL: test_mfence:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: mfence # sched: [1:1.00] ; SLM-NEXT: mfence # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
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; BTVER2-LABEL: test_mfence: ; BTVER2-LABEL: test_mfence:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: mfence # sched: [1:1.00] ; BTVER2-NEXT: mfence # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_mfence: ; ZNVER1-LABEL: test_mfence:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: mfence # sched: [1:0.50] ; ZNVER1-NEXT: mfence # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
call void @llvm.x86.sse2.mfence() call void @llvm.x86.sse2.mfence()
ret void ret void
} }
declare void @llvm.x86.sse2.mfence() nounwind readnone declare void @llvm.x86.sse2.mfence() nounwind readnone
define void @test_maskmovdqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) { define void @test_maskmovdqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) {
; GENERIC-LABEL: test_maskmovdqu: ; GENERIC-LABEL: test_maskmovdqu:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: maskmovdqu %xmm1, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: maskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_maskmovdqu: ; ATOM-LABEL: test_maskmovdqu:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: maskmovdqu %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: maskmovdqu %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_maskmovdqu: ; SLM-LABEL: test_maskmovdqu:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: maskmovdqu %xmm1, %xmm0 # sched: [1:1.00] ; SLM-NEXT: maskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
Show All 11 Lines
; ;
; BTVER2-LABEL: test_maskmovdqu: ; BTVER2-LABEL: test_maskmovdqu:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00] ; BTVER2-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_maskmovdqu: ; ZNVER1-LABEL: test_maskmovdqu:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:0.50] ; ZNVER1-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [100:?]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
call void @llvm.x86.sse2.maskmov.dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) call void @llvm.x86.sse2.maskmov.dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2)
ret void ret void
} }
declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind
define <2 x double> @test_maxpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_maxpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_maxpd: ; GENERIC-LABEL: test_maxpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: maxpd %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: maxpd %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: maxpd (%rdi), %xmm0 # sched: [9:1.00] ; GENERIC-NEXT: maxpd (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_maxpd: ; ATOM-LABEL: test_maxpd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: maxpd %xmm1, %xmm0 # sched: [6:3.00] ; ATOM-NEXT: maxpd %xmm1, %xmm0 # sched: [6:3.00]
; ATOM-NEXT: maxpd (%rdi), %xmm0 # sched: [7:3.50] ; ATOM-NEXT: maxpd (%rdi), %xmm0 # sched: [7:3.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_maxpd: ; SLM-LABEL: test_maxpd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: maxpd %xmm1, %xmm0 # sched: [3:1.00] ; SLM-NEXT: maxpd %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: maxpd (%rdi), %xmm0 # sched: [6:1.00] ; SLM-NEXT: maxpd (%rdi), %xmm0 # sched: [6:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_maxpd: ; SANDY-LABEL: test_maxpd:
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; BTVER2-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_maxpd: ; ZNVER1-LABEL: test_maxpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) %1 = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1)
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %1, <2 x double> %2) %3 = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %1, <2 x double> %2)
ret <2 x double> %3 ret <2 x double> %3
} }
declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
define <2 x double> @test_maxsd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_maxsd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_maxsd: ; GENERIC-LABEL: test_maxsd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: maxsd %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: maxsd %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: maxsd (%rdi), %xmm0 # sched: [9:1.00] ; GENERIC-NEXT: maxsd (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_maxsd: ; ATOM-LABEL: test_maxsd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: maxsd %xmm1, %xmm0 # sched: [5:5.00] ; ATOM-NEXT: maxsd %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: maxsd (%rdi), %xmm0 # sched: [5:5.00] ; ATOM-NEXT: maxsd (%rdi), %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_maxsd: ; SLM-LABEL: test_maxsd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: maxsd %xmm1, %xmm0 # sched: [3:1.00] ; SLM-NEXT: maxsd %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: maxsd (%rdi), %xmm0 # sched: [6:1.00] ; SLM-NEXT: maxsd (%rdi), %xmm0 # sched: [6:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
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; BTVER2-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_maxsd: ; ZNVER1-LABEL: test_maxsd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) %1 = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1)
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %1, <2 x double> %2) %3 = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %1, <2 x double> %2)
ret <2 x double> %3 ret <2 x double> %3
} }
declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
define <2 x double> @test_minpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_minpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_minpd: ; GENERIC-LABEL: test_minpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: minpd %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: minpd %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: minpd (%rdi), %xmm0 # sched: [9:1.00] ; GENERIC-NEXT: minpd (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_minpd: ; ATOM-LABEL: test_minpd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: minpd %xmm1, %xmm0 # sched: [6:3.00] ; ATOM-NEXT: minpd %xmm1, %xmm0 # sched: [6:3.00]
; ATOM-NEXT: minpd (%rdi), %xmm0 # sched: [7:3.50] ; ATOM-NEXT: minpd (%rdi), %xmm0 # sched: [7:3.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_minpd: ; SLM-LABEL: test_minpd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: minpd %xmm1, %xmm0 # sched: [3:1.00] ; SLM-NEXT: minpd %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: minpd (%rdi), %xmm0 # sched: [6:1.00] ; SLM-NEXT: minpd (%rdi), %xmm0 # sched: [6:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
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; BTVER2-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_minpd: ; ZNVER1-LABEL: test_minpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) %1 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1)
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %1, <2 x double> %2) %3 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %1, <2 x double> %2)
ret <2 x double> %3 ret <2 x double> %3
} }
declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
define <2 x double> @test_minsd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_minsd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_minsd: ; GENERIC-LABEL: test_minsd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: minsd %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: minsd %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: minsd (%rdi), %xmm0 # sched: [9:1.00] ; GENERIC-NEXT: minsd (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_minsd: ; ATOM-LABEL: test_minsd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: minsd %xmm1, %xmm0 # sched: [5:5.00] ; ATOM-NEXT: minsd %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: minsd (%rdi), %xmm0 # sched: [5:5.00] ; ATOM-NEXT: minsd (%rdi), %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_minsd: ; SLM-LABEL: test_minsd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: minsd %xmm1, %xmm0 # sched: [3:1.00] ; SLM-NEXT: minsd %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: minsd (%rdi), %xmm0 # sched: [6:1.00] ; SLM-NEXT: minsd (%rdi), %xmm0 # sched: [6:1.00]
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; BTVER2-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_minsd: ; ZNVER1-LABEL: test_minsd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00] ; ZNVER1-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) %1 = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1)
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %1, <2 x double> %2) %3 = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %1, <2 x double> %2)
ret <2 x double> %3 ret <2 x double> %3
} }
declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
define void @test_movapd(<2 x double> *%a0, <2 x double> *%a1) { define void @test_movapd(<2 x double> *%a0, <2 x double> *%a1) {
; GENERIC-LABEL: test_movapd: ; GENERIC-LABEL: test_movapd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movapd (%rdi), %xmm0 # sched: [6:0.50] ; GENERIC-NEXT: movapd (%rdi), %xmm0 # sched: [6:0.50]
; GENERIC-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: movapd %xmm0, (%rsi) # sched: [5:1.00] ; GENERIC-NEXT: movapd %xmm0, (%rsi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movapd: ; ATOM-LABEL: test_movapd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: movapd (%rdi), %xmm0 # sched: [1:1.00] ; ATOM-NEXT: movapd (%rdi), %xmm0 # sched: [1:1.00]
; ATOM-NEXT: addpd %xmm0, %xmm0 # sched: [6:3.00] ; ATOM-NEXT: addpd %xmm0, %xmm0 # sched: [6:3.00]
; ATOM-NEXT: movapd %xmm0, (%rsi) # sched: [1:1.00] ; ATOM-NEXT: movapd %xmm0, (%rsi) # sched: [1:1.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_movapd: ; SLM-LABEL: test_movapd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: movapd (%rdi), %xmm0 # sched: [3:1.00] ; SLM-NEXT: movapd (%rdi), %xmm0 # sched: [3:1.00]
; SLM-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00] ; SLM-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00]
; SLM-NEXT: movapd %xmm0, (%rsi) # sched: [1:1.00] ; SLM-NEXT: movapd %xmm0, (%rsi) # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_movapd: ; SANDY-LABEL: test_movapd:
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; BTVER2-NEXT: vmovapd %xmm0, (%rsi) # sched: [1:1.00] ; BTVER2-NEXT: vmovapd %xmm0, (%rsi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movapd: ; ZNVER1-LABEL: test_movapd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovapd (%rdi), %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vmovapd (%rdi), %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmovapd %xmm0, (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovapd %xmm0, (%rsi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x double>, <2 x double> *%a0, align 16 %1 = load <2 x double>, <2 x double> *%a0, align 16
%2 = fadd <2 x double> %1, %1 %2 = fadd <2 x double> %1, %1
store <2 x double> %2, <2 x double> *%a1, align 16 store <2 x double> %2, <2 x double> *%a1, align 16
ret void ret void
} }
define void @test_movdqa(<2 x i64> *%a0, <2 x i64> *%a1) { define void @test_movdqa(<2 x i64> *%a0, <2 x i64> *%a1) {
; GENERIC-LABEL: test_movdqa: ; GENERIC-LABEL: test_movdqa:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movdqa (%rdi), %xmm0 # sched: [6:0.50] ; GENERIC-NEXT: movdqa (%rdi), %xmm0 # sched: [6:0.50]
; GENERIC-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: movdqa %xmm0, (%rsi) # sched: [5:1.00] ; GENERIC-NEXT: movdqa %xmm0, (%rsi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movdqa: ; ATOM-LABEL: test_movdqa:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: movdqa (%rdi), %xmm0 # sched: [1:1.00] ; ATOM-NEXT: movdqa (%rdi), %xmm0 # sched: [1:1.00]
; ATOM-NEXT: paddq %xmm0, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: paddq %xmm0, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: movdqa %xmm0, (%rsi) # sched: [1:1.00] ; ATOM-NEXT: movdqa %xmm0, (%rsi) # sched: [1:1.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_movdqa: ; SLM-LABEL: test_movdqa:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: movdqa (%rdi), %xmm0 # sched: [3:1.00] ; SLM-NEXT: movdqa (%rdi), %xmm0 # sched: [3:1.00]
; SLM-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50] ; SLM-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50]
; SLM-NEXT: movdqa %xmm0, (%rsi) # sched: [1:1.00] ; SLM-NEXT: movdqa %xmm0, (%rsi) # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
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; BTVER2-NEXT: vmovdqa %xmm0, (%rsi) # sched: [1:1.00] ; BTVER2-NEXT: vmovdqa %xmm0, (%rsi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movdqa: ; ZNVER1-LABEL: test_movdqa:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovdqa (%rdi), %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vmovdqa (%rdi), %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vmovdqa %xmm0, (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovdqa %xmm0, (%rsi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a0, align 16 %1 = load <2 x i64>, <2 x i64> *%a0, align 16
%2 = add <2 x i64> %1, %1 %2 = add <2 x i64> %1, %1
store <2 x i64> %2, <2 x i64> *%a1, align 16 store <2 x i64> %2, <2 x i64> *%a1, align 16
ret void ret void
} }
define void @test_movdqu(<2 x i64> *%a0, <2 x i64> *%a1) { define void @test_movdqu(<2 x i64> *%a0, <2 x i64> *%a1) {
; GENERIC-LABEL: test_movdqu: ; GENERIC-LABEL: test_movdqu:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movdqu (%rdi), %xmm0 # sched: [6:0.50] ; GENERIC-NEXT: movdqu (%rdi), %xmm0 # sched: [6:0.50]
; GENERIC-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: movdqu %xmm0, (%rsi) # sched: [5:1.00] ; GENERIC-NEXT: movdqu %xmm0, (%rsi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movdqu: ; ATOM-LABEL: test_movdqu:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: movdqu (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: movdqu (%rdi), %xmm0 # sched: [3:1.50]
; ATOM-NEXT: paddq %xmm0, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: paddq %xmm0, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: movdqu %xmm0, (%rsi) # sched: [2:1.00] ; ATOM-NEXT: movdqu %xmm0, (%rsi) # sched: [2:1.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_movdqu: ; SLM-LABEL: test_movdqu:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: movdqu (%rdi), %xmm0 # sched: [3:1.00] ; SLM-NEXT: movdqu (%rdi), %xmm0 # sched: [3:1.00]
; SLM-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50] ; SLM-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50]
; SLM-NEXT: movdqu %xmm0, (%rsi) # sched: [1:1.00] ; SLM-NEXT: movdqu %xmm0, (%rsi) # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
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; BTVER2-NEXT: vmovdqu %xmm0, (%rsi) # sched: [1:1.00] ; BTVER2-NEXT: vmovdqu %xmm0, (%rsi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movdqu: ; ZNVER1-LABEL: test_movdqu:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovdqu (%rdi), %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vmovdqu (%rdi), %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vmovdqu %xmm0, (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovdqu %xmm0, (%rsi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a0, align 1 %1 = load <2 x i64>, <2 x i64> *%a0, align 1
%2 = add <2 x i64> %1, %1 %2 = add <2 x i64> %1, %1
store <2 x i64> %2, <2 x i64> *%a1, align 1 store <2 x i64> %2, <2 x i64> *%a1, align 1
ret void ret void
} }
define i32 @test_movd(<4 x i32> %a0, i32 %a1, i32 *%a2) { define i32 @test_movd(<4 x i32> %a0, i32 %a1, i32 *%a2) {
; GENERIC-LABEL: test_movd: ; GENERIC-LABEL: test_movd:
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; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_movd: ; SLM-LABEL: test_movd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [3:1.00] ; SLM-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [3:1.00]
; SLM-NEXT: movd %edi, %xmm1 # sched: [1:0.50] ; SLM-NEXT: movd %edi, %xmm1 # sched: [1:0.50]
; SLM-NEXT: paddd %xmm0, %xmm1 # sched: [1:0.50] ; SLM-NEXT: paddd %xmm0, %xmm1 # sched: [1:0.50]
; SLM-NEXT: movd %xmm1, (%rsi) # sched: [1:1.00] ; SLM-NEXT: movd %xmm1, (%rsi) # sched: [1:1.00]
; SLM-NEXT: paddd %xmm0, %xmm2 # sched: [1:0.50] ; SLM-NEXT: paddd %xmm0, %xmm2 # sched: [1:0.50]
; SLM-NEXT: movd %xmm2, %eax # sched: [1:0.50] ; SLM-NEXT: movd %xmm2, %eax # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_movd: ; SANDY-LABEL: test_movd:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vmovd %edi, %xmm1 # sched: [1:1.00] ; SANDY-NEXT: vmovd %edi, %xmm1 # sched: [1:1.00]
; SANDY-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [6:0.50] ; SANDY-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [6:0.50]
; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; SANDY-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: vmovd %xmm0, %eax # sched: [2:1.00] ; SANDY-NEXT: vmovd %xmm0, %eax # sched: [2:1.00]
; SANDY-NEXT: vmovd %xmm1, (%rsi) # sched: [5:1.00] ; SANDY-NEXT: vmovd %xmm1, (%rsi) # sched: [5:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
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; BTVER2-NEXT: vmovd %xmm1, (%rsi) # sched: [1:1.00] ; BTVER2-NEXT: vmovd %xmm1, (%rsi) # sched: [1:1.00]
; BTVER2-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vmovd %xmm0, %eax # sched: [1:0.17] ; BTVER2-NEXT: vmovd %xmm0, %eax # sched: [1:0.17]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movd: ; ZNVER1-LABEL: test_movd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [8:0.50] ; ZNVER1-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [8:0.50]
; ZNVER1-NEXT: vmovd %edi, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vmovd %edi, %xmm1 # sched: [3:1.00]
; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vmovd %xmm1, (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovd %xmm1, (%rsi) # sched: [1:0.50]
; ZNVER1-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vmovd %xmm0, %eax # sched: [1:0.25] ; ZNVER1-NEXT: vmovd %xmm0, %eax # sched: [2:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = insertelement <4 x i32> undef, i32 %a1, i32 0 %1 = insertelement <4 x i32> undef, i32 %a1, i32 0
%2 = load i32, i32 *%a2 %2 = load i32, i32 *%a2
%3 = insertelement <4 x i32> undef, i32 %2, i32 0 %3 = insertelement <4 x i32> undef, i32 %2, i32 0
%4 = add <4 x i32> %a0, %1 %4 = add <4 x i32> %a0, %1
%5 = add <4 x i32> %a0, %3 %5 = add <4 x i32> %a0, %3
%6 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 0
%7 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 0
store i32 %6, i32* %a2 store i32 %6, i32* %a2
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; ATOM-NEXT: movq %xmm1, %rax # sched: [3:3.00] ; ATOM-NEXT: movq %xmm1, %rax # sched: [3:3.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_movd_64: ; SLM-LABEL: test_movd_64:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: movq {{.*#+}} xmm2 = mem[0],zero sched: [3:1.00] ; SLM-NEXT: movq {{.*#+}} xmm2 = mem[0],zero sched: [3:1.00]
; SLM-NEXT: movq %rdi, %xmm1 # sched: [1:0.50] ; SLM-NEXT: movq %rdi, %xmm1 # sched: [1:0.50]
; SLM-NEXT: paddq %xmm0, %xmm1 # sched: [1:0.50] ; SLM-NEXT: paddq %xmm0, %xmm1 # sched: [1:0.50]
; SLM-NEXT: movq %xmm1, (%rsi) # sched: [1:1.00] ; SLM-NEXT: movq %xmm1, (%rsi) # sched: [1:1.00]
; SLM-NEXT: paddq %xmm0, %xmm2 # sched: [1:0.50] ; SLM-NEXT: paddq %xmm0, %xmm2 # sched: [1:0.50]
; SLM-NEXT: movq %xmm2, %rax # sched: [1:0.50] ; SLM-NEXT: movq %xmm2, %rax # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_movd_64: ; SANDY-LABEL: test_movd_64:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vmovq %rdi, %xmm1 # sched: [1:1.00] ; SANDY-NEXT: vmovq %rdi, %xmm1 # sched: [1:1.00]
; SANDY-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [6:0.50] ; SANDY-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [6:0.50]
; SANDY-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; SANDY-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; SANDY-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: vmovq %xmm0, %rax # sched: [2:1.00] ; SANDY-NEXT: vmovq %xmm0, %rax # sched: [2:1.00]
; SANDY-NEXT: vmovq %xmm1, (%rsi) # sched: [5:1.00] ; SANDY-NEXT: vmovq %xmm1, (%rsi) # sched: [5:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
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; BTVER2-NEXT: vmovq %xmm1, (%rsi) # sched: [1:1.00] ; BTVER2-NEXT: vmovq %xmm1, (%rsi) # sched: [1:1.00]
; BTVER2-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vmovq %xmm0, %rax # sched: [1:0.17] ; BTVER2-NEXT: vmovq %xmm0, %rax # sched: [1:0.17]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movd_64: ; ZNVER1-LABEL: test_movd_64:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [8:0.50] ; ZNVER1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [8:0.50]
; ZNVER1-NEXT: vmovq %rdi, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vmovq %rdi, %xmm1 # sched: [3:1.00]
; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vmovq %xmm1, (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovq %xmm1, (%rsi) # sched: [1:0.50]
; ZNVER1-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vmovq %xmm0, %rax # sched: [1:0.25] ; ZNVER1-NEXT: vmovq %xmm0, %rax # sched: [2:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = insertelement <2 x i64> undef, i64 %a1, i64 0 %1 = insertelement <2 x i64> undef, i64 %a1, i64 0
%2 = load i64, i64 *%a2 %2 = load i64, i64 *%a2
%3 = insertelement <2 x i64> undef, i64 %2, i64 0 %3 = insertelement <2 x i64> undef, i64 %2, i64 0
%4 = add <2 x i64> %a0, %1 %4 = add <2 x i64> %a0, %1
%5 = add <2 x i64> %a0, %3 %5 = add <2 x i64> %a0, %3
%6 = extractelement <2 x i64> %4, i64 0 %6 = extractelement <2 x i64> %4, i64 0
%7 = extractelement <2 x i64> %5, i64 0 %7 = extractelement <2 x i64> %5, i64 0
store i64 %6, i64* %a2 store i64 %6, i64* %a2
ret i64 %7 ret i64 %7
} }
define void @test_movhpd(<2 x double> %a0, <2 x double> %a1, x86_mmx *%a2) { define void @test_movhpd(<2 x double> %a0, <2 x double> %a1, x86_mmx *%a2) {
; GENERIC-LABEL: test_movhpd: ; GENERIC-LABEL: test_movhpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [7:1.00] ; GENERIC-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [7:1.00]
; GENERIC-NEXT: addpd %xmm0, %xmm1 # sched: [3:1.00] ; GENERIC-NEXT: addpd %xmm0, %xmm1 # sched: [3:1.00]
; GENERIC-NEXT: movhpd %xmm1, (%rdi) # sched: [5:1.00] ; GENERIC-NEXT: movhpd %xmm1, (%rdi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movhpd: ; ATOM-LABEL: test_movhpd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00] ; ATOM-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]
; ATOM-NEXT: addpd %xmm0, %xmm1 # sched: [6:3.00] ; ATOM-NEXT: addpd %xmm0, %xmm1 # sched: [6:3.00]
; ATOM-NEXT: movhpd %xmm1, (%rdi) # sched: [1:1.00] ; ATOM-NEXT: movhpd %xmm1, (%rdi) # sched: [1:1.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_movhpd: ; SLM-LABEL: test_movhpd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [4:1.00] ; SLM-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [4:1.00]
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; BTVER2-NEXT: vmovhpd %xmm0, (%rdi) # sched: [1:1.00] ; BTVER2-NEXT: vmovhpd %xmm0, (%rdi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movhpd: ; ZNVER1-LABEL: test_movhpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [8:0.50] ; ZNVER1-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [8:0.50]
; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmovhpd %xmm0, (%rdi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovhpd %xmm0, (%rdi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = bitcast x86_mmx* %a2 to double* %1 = bitcast x86_mmx* %a2 to double*
%2 = load double, double *%1, align 8 %2 = load double, double *%1, align 8
%3 = insertelement <2 x double> %a1, double %2, i32 1 %3 = insertelement <2 x double> %a1, double %2, i32 1
%4 = fadd <2 x double> %a0, %3 %4 = fadd <2 x double> %a0, %3
%5 = extractelement <2 x double> %4, i32 1 %5 = extractelement <2 x double> %4, i32 1
store double %5, double* %1 store double %5, double* %1
ret void ret void
} }
define void @test_movlpd(<2 x double> %a0, <2 x double> %a1, x86_mmx *%a2) { define void @test_movlpd(<2 x double> %a0, <2 x double> %a1, x86_mmx *%a2) {
; GENERIC-LABEL: test_movlpd: ; GENERIC-LABEL: test_movlpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [7:1.00] ; GENERIC-NEXT: movlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [7:1.00]
; GENERIC-NEXT: addpd %xmm0, %xmm1 # sched: [3:1.00] ; GENERIC-NEXT: addpd %xmm0, %xmm1 # sched: [3:1.00]
; GENERIC-NEXT: movlpd %xmm1, (%rdi) # sched: [5:1.00] ; GENERIC-NEXT: movlpd %xmm1, (%rdi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movlpd: ; ATOM-LABEL: test_movlpd:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: movlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00] ; ATOM-NEXT: movlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]
; ATOM-NEXT: addpd %xmm0, %xmm1 # sched: [6:3.00] ; ATOM-NEXT: addpd %xmm0, %xmm1 # sched: [6:3.00]
; ATOM-NEXT: movlpd %xmm1, (%rdi) # sched: [1:1.00] ; ATOM-NEXT: movlpd %xmm1, (%rdi) # sched: [1:1.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_movlpd: ; SLM-LABEL: test_movlpd:
; SLM: # BB#0: ; SLM: # BB#0:
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; BTVER2-NEXT: vmovlpd %xmm0, (%rdi) # sched: [1:1.00] ; BTVER2-NEXT: vmovlpd %xmm0, (%rdi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movlpd: ; ZNVER1-LABEL: test_movlpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [8:0.50] ; ZNVER1-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [8:0.50]
; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmovlpd %xmm0, (%rdi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovlpd %xmm0, (%rdi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = bitcast x86_mmx* %a2 to double* %1 = bitcast x86_mmx* %a2 to double*
%2 = load double, double *%1, align 8 %2 = load double, double *%1, align 8
%3 = insertelement <2 x double> %a1, double %2, i32 0 %3 = insertelement <2 x double> %a1, double %2, i32 0
%4 = fadd <2 x double> %a0, %3 %4 = fadd <2 x double> %a0, %3
%5 = extractelement <2 x double> %4, i32 0 %5 = extractelement <2 x double> %4, i32 0
store double %5, double* %1 store double %5, double* %1
ret void ret void
} }
define i32 @test_movmskpd(<2 x double> %a0) { define i32 @test_movmskpd(<2 x double> %a0) {
; GENERIC-LABEL: test_movmskpd: ; GENERIC-LABEL: test_movmskpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movmskpd %xmm0, %eax # sched: [2:1.00] ; GENERIC-NEXT: movmskpd %xmm0, %eax # sched: [2:1.00]
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; ;
; BTVER2-LABEL: test_movmskpd: ; BTVER2-LABEL: test_movmskpd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vmovmskpd %xmm0, %eax # sched: [1:0.50] ; BTVER2-NEXT: vmovmskpd %xmm0, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movmskpd: ; ZNVER1-LABEL: test_movmskpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovmskpd %xmm0, %eax # sched: [1:0.25] ; ZNVER1-NEXT: vmovmskpd %xmm0, %eax # sched: [1:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) %1 = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0)
ret i32 %1 ret i32 %1
} }
declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
define void @test_movntdqa(<2 x i64> %a0, <2 x i64> *%a1) { define void @test_movntdqa(<2 x i64> %a0, <2 x i64> *%a1) {
; GENERIC-LABEL: test_movntdqa: ; GENERIC-LABEL: test_movntdqa:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: paddq %xmm0, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: movntdq %xmm0, (%rdi) # sched: [5:1.00] ; GENERIC-NEXT: movntdq %xmm0, (%rdi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movntdqa: ; ATOM-LABEL: test_movntdqa:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: paddq %xmm0, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: paddq %xmm0, %xmm0 # sched: [2:1.00]
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; BTVER2-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vmovntdq %xmm0, (%rdi) # sched: [1:1.00] ; BTVER2-NEXT: vmovntdq %xmm0, (%rdi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movntdqa: ; ZNVER1-LABEL: test_movntdqa:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vmovntdq %xmm0, (%rdi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovntdq %xmm0, (%rdi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = add <2 x i64> %a0, %a0 %1 = add <2 x i64> %a0, %a0
store <2 x i64> %1, <2 x i64> *%a1, align 16, !nontemporal !0 store <2 x i64> %1, <2 x i64> *%a1, align 16, !nontemporal !0
ret void ret void
} }
define void @test_movntpd(<2 x double> %a0, <2 x double> *%a1) { define void @test_movntpd(<2 x double> %a0, <2 x double> *%a1) {
; GENERIC-LABEL: test_movntpd: ; GENERIC-LABEL: test_movntpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: movntpd %xmm0, (%rdi) # sched: [5:1.00] ; GENERIC-NEXT: movntpd %xmm0, (%rdi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
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; BTVER2-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vmovntpd %xmm0, (%rdi) # sched: [1:1.00] ; BTVER2-NEXT: vmovntpd %xmm0, (%rdi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movntpd: ; ZNVER1-LABEL: test_movntpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmovntpd %xmm0, (%rdi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovntpd %xmm0, (%rdi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fadd <2 x double> %a0, %a0 %1 = fadd <2 x double> %a0, %a0
store <2 x double> %1, <2 x double> *%a1, align 16, !nontemporal !0 store <2 x double> %1, <2 x double> *%a1, align 16, !nontemporal !0
ret void ret void
} }
define <2 x i64> @test_movq_mem(<2 x i64> %a0, i64 *%a1) { define <2 x i64> @test_movq_mem(<2 x i64> %a0, i64 *%a1) {
; GENERIC-LABEL: test_movq_mem: ; GENERIC-LABEL: test_movq_mem:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movq {{.*#+}} xmm1 = mem[0],zero sched: [4:0.50] ; GENERIC-NEXT: movq {{.*#+}} xmm1 = mem[0],zero sched: [4:0.50]
; GENERIC-NEXT: paddq %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: paddq %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: movq %xmm0, (%rdi) # sched: [5:1.00] ; GENERIC-NEXT: movq %xmm0, (%rdi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movq_mem: ; ATOM-LABEL: test_movq_mem:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: movq {{.*#+}} xmm1 = mem[0],zero sched: [1:1.00] ; ATOM-NEXT: movq {{.*#+}} xmm1 = mem[0],zero sched: [1:1.00]
; ATOM-NEXT: paddq %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: paddq %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: movq %xmm0, (%rdi) # sched: [1:1.00] ; ATOM-NEXT: movq %xmm0, (%rdi) # sched: [1:1.00]
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; BTVER2-NEXT: vmovq %xmm0, (%rdi) # sched: [1:1.00] ; BTVER2-NEXT: vmovq %xmm0, (%rdi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movq_mem: ; ZNVER1-LABEL: test_movq_mem:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero sched: [8:0.50] ; ZNVER1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero sched: [8:0.50]
; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vmovq %xmm0, (%rdi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovq %xmm0, (%rdi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load i64, i64* %a1, align 1 %1 = load i64, i64* %a1, align 1
%2 = insertelement <2 x i64> zeroinitializer, i64 %1, i32 0 %2 = insertelement <2 x i64> zeroinitializer, i64 %1, i32 0
%3 = add <2 x i64> %a0, %2 %3 = add <2 x i64> %a0, %2
%4 = extractelement <2 x i64> %3, i32 0 %4 = extractelement <2 x i64> %3, i32 0
store i64 %4, i64 *%a1, align 1 store i64 %4, i64 *%a1, align 1
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <2 x i64> @test_movq_reg(<2 x i64> %a0, <2 x i64> %a1) { define <2 x i64> @test_movq_reg(<2 x i64> %a0, <2 x i64> %a1) {
; GENERIC-LABEL: test_movq_reg: ; GENERIC-LABEL: test_movq_reg:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:1.00] ; GENERIC-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:1.00]
; GENERIC-NEXT: paddq %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: paddq %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
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; BTVER2-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.50] ; BTVER2-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.50]
; BTVER2-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movq_reg: ; ZNVER1-LABEL: test_movq_reg:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.25] ; ZNVER1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.25]
; ZNVER1-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2> %1 = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
%2 = add <2 x i64> %a1, %1 %2 = add <2 x i64> %a1, %1
ret <2 x i64> %2 ret <2 x i64> %2
} }
define void @test_movsd_mem(double* %a0, double* %a1) { define void @test_movsd_mem(double* %a0, double* %a1) {
; GENERIC-LABEL: test_movsd_mem: ; GENERIC-LABEL: test_movsd_mem:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero sched: [4:0.50] ; GENERIC-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero sched: [4:0.50]
; GENERIC-NEXT: addsd %xmm0, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: addsd %xmm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: movsd %xmm0, (%rsi) # sched: [1:1.00] ; GENERIC-NEXT: movsd %xmm0, (%rsi) # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movsd_mem: ; ATOM-LABEL: test_movsd_mem:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero sched: [1:1.00] ; ATOM-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero sched: [1:1.00]
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; BTVER2-NEXT: vmovsd %xmm0, (%rsi) # sched: [1:1.00] ; BTVER2-NEXT: vmovsd %xmm0, (%rsi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movsd_mem: ; ZNVER1-LABEL: test_movsd_mem:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [8:0.50] ; ZNVER1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [8:0.50]
; ZNVER1-NEXT: vaddsd %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddsd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmovsd %xmm0, (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovsd %xmm0, (%rsi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load double, double* %a0, align 1 %1 = load double, double* %a0, align 1
%2 = fadd double %1, %1 %2 = fadd double %1, %1
store double %2, double *%a1, align 1 store double %2, double *%a1, align 1
ret void ret void
} }
define <2 x double> @test_movsd_reg(<2 x double> %a0, <2 x double> %a1) { define <2 x double> @test_movsd_reg(<2 x double> %a0, <2 x double> %a1) {
; GENERIC-LABEL: test_movsd_reg: ; GENERIC-LABEL: test_movsd_reg:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
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; BTVER2-LABEL: test_movsd_reg: ; BTVER2-LABEL: test_movsd_reg:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] sched: [1:0.50] ; BTVER2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movsd_reg: ; ZNVER1-LABEL: test_movsd_reg:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] sched: [1:0.50] ; ZNVER1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 2, i32 0> %1 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 2, i32 0>
ret <2 x double> %1 ret <2 x double> %1
} }
define void @test_movupd(<2 x double> *%a0, <2 x double> *%a1) { define void @test_movupd(<2 x double> *%a0, <2 x double> *%a1) {
; GENERIC-LABEL: test_movupd: ; GENERIC-LABEL: test_movupd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: movupd (%rdi), %xmm0 # sched: [6:0.50] ; GENERIC-NEXT: movupd (%rdi), %xmm0 # sched: [6:0.50]
; GENERIC-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: addpd %xmm0, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: movupd %xmm0, (%rsi) # sched: [5:1.00] ; GENERIC-NEXT: movupd %xmm0, (%rsi) # sched: [5:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_movupd: ; ATOM-LABEL: test_movupd:
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vmovupd (%rdi), %xmm0 # sched: [5:1.00] ; BTVER2-NEXT: vmovupd (%rdi), %xmm0 # sched: [5:1.00]
; BTVER2-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vmovupd %xmm0, (%rsi) # sched: [1:1.00] ; BTVER2-NEXT: vmovupd %xmm0, (%rsi) # sched: [1:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_movupd: ; ZNVER1-LABEL: test_movupd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmovupd (%rdi), %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vmovupd (%rdi), %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: vmovupd %xmm0, (%rsi) # sched: [1:0.50] ; ZNVER1-NEXT: vmovupd %xmm0, (%rsi) # sched: [1:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x double>, <2 x double> *%a0, align 1 %1 = load <2 x double>, <2 x double> *%a0, align 1
%2 = fadd <2 x double> %1, %1 %2 = fadd <2 x double> %1, %1
store <2 x double> %2, <2 x double> *%a1, align 1 store <2 x double> %2, <2 x double> *%a1, align 1
ret void ret void
} }
define <2 x double> @test_mulpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_mulpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_mulpd: ; GENERIC-LABEL: test_mulpd:
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; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_mulpd: ; BTVER2-LABEL: test_mulpd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vmulpd %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vmulpd %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_mulpd: ; ZNVER1-LABEL: test_mulpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmulpd %xmm1, %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vmulpd %xmm1, %xmm0, %xmm0 # sched: [3:0.50]
; ZNVER1-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [12:1.00] ; ZNVER1-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fmul <2 x double> %a0, %a1 %1 = fmul <2 x double> %a0, %a1
%2 = load <2 x double>, <2 x double> *%a2, align 16 %2 = load <2 x double>, <2 x double> *%a2, align 16
%3 = fmul <2 x double> %1, %2 %3 = fmul <2 x double> %1, %2
ret <2 x double> %3 ret <2 x double> %3
} }
define double @test_mulsd(double %a0, double %a1, double *%a2) { define double @test_mulsd(double %a0, double %a1, double *%a2) {
; GENERIC-LABEL: test_mulsd: ; GENERIC-LABEL: test_mulsd:
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; BTVER2-LABEL: test_mulsd: ; BTVER2-LABEL: test_mulsd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vmulsd %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vmulsd %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_mulsd: ; ZNVER1-LABEL: test_mulsd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vmulsd %xmm1, %xmm0, %xmm0 # sched: [5:1.00] ; ZNVER1-NEXT: vmulsd %xmm1, %xmm0, %xmm0 # sched: [3:0.50]
; ZNVER1-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [12:1.00] ; ZNVER1-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = fmul double %a0, %a1 %1 = fmul double %a0, %a1
%2 = load double, double *%a2, align 8 %2 = load double, double *%a2, align 8
%3 = fmul double %1, %2 %3 = fmul double %1, %2
ret double %3 ret double %3
} }
define <2 x double> @test_orpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) { define <2 x double> @test_orpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
; GENERIC-LABEL: test_orpd: ; GENERIC-LABEL: test_orpd:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: orpd %xmm1, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: orpd %xmm1, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: orpd (%rdi), %xmm0 # sched: [7:1.00] ; GENERIC-NEXT: orpd (%rdi), %xmm0 # sched: [7:1.00]
; GENERIC-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
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; BTVER2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_orpd: ; ZNVER1-LABEL: test_orpd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vorpd (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vorpd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00] ; ZNVER1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = bitcast <2 x double> %a0 to <4 x i32> %1 = bitcast <2 x double> %a0 to <4 x i32>
%2 = bitcast <2 x double> %a1 to <4 x i32> %2 = bitcast <2 x double> %a1 to <4 x i32>
%3 = or <4 x i32> %1, %2 %3 = or <4 x i32> %1, %2
%4 = load <2 x double>, <2 x double> *%a2, align 16 %4 = load <2 x double>, <2 x double> *%a2, align 16
%5 = bitcast <2 x double> %4 to <4 x i32> %5 = bitcast <2 x double> %4 to <4 x i32>
%6 = or <4 x i32> %3, %5 %6 = or <4 x i32> %3, %5
%7 = bitcast <4 x i32> %6 to <2 x double> %7 = bitcast <4 x i32> %6 to <2 x double>
%8 = fadd <2 x double> %a1, %7 %8 = fadd <2 x double> %a1, %7
ret <2 x double> %8 ret <2 x double> %8
} }
define <8 x i16> @test_packssdw(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { define <8 x i16> @test_packssdw(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
; GENERIC-LABEL: test_packssdw: ; GENERIC-LABEL: test_packssdw:
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; BTVER2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_packssdw: ; ZNVER1-LABEL: test_packssdw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) %1 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1)
%2 = bitcast <8 x i16> %1 to <4 x i32> %2 = bitcast <8 x i16> %1 to <4 x i32>
%3 = load <4 x i32>, <4 x i32> *%a2, align 16 %3 = load <4 x i32>, <4 x i32> *%a2, align 16
%4 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %2, <4 x i32> %3) %4 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %2, <4 x i32> %3)
ret <8 x i16> %4 ret <8 x i16> %4
} }
declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone
define <16 x i8> @test_packsswb(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <16 x i8> @test_packsswb(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; BTVER2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_packsswb: ; ZNVER1-LABEL: test_packsswb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) %1 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1)
%2 = bitcast <16 x i8> %1 to <8 x i16> %2 = bitcast <16 x i8> %1 to <8 x i16>
%3 = load <8 x i16>, <8 x i16> *%a2, align 16 %3 = load <8 x i16>, <8 x i16> *%a2, align 16
%4 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %2, <8 x i16> %3) %4 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %2, <8 x i16> %3)
ret <16 x i8> %4 ret <16 x i8> %4
} }
declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_packuswb: ; ZNVER1-LABEL: test_packuswb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) %1 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1)
%2 = bitcast <16 x i8> %1 to <8 x i16> %2 = bitcast <16 x i8> %1 to <8 x i16>
%3 = load <8 x i16>, <8 x i16> *%a2, align 16 %3 = load <8 x i16>, <8 x i16> *%a2, align 16
%4 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %2, <8 x i16> %3) %4 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %2, <8 x i16> %3)
ret <16 x i8> %4 ret <16 x i8> %4
} }
declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone
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; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddb: ; BTVER2-LABEL: test_paddb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddb: ; ZNVER1-LABEL: test_paddb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = add <16 x i8> %a0, %a1 %1 = add <16 x i8> %a0, %a1
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = add <16 x i8> %1, %2 %3 = add <16 x i8> %1, %2
ret <16 x i8> %3 ret <16 x i8> %3
} }
define <4 x i32> @test_paddd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { define <4 x i32> @test_paddd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
; GENERIC-LABEL: test_paddd: ; GENERIC-LABEL: test_paddd:
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; ;
; HASWELL-LABEL: test_paddd: ; HASWELL-LABEL: test_paddd:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddd: ; BTVER2-LABEL: test_paddd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddd: ; ZNVER1-LABEL: test_paddd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = add <4 x i32> %a0, %a1 %1 = add <4 x i32> %a0, %a1
%2 = load <4 x i32>, <4 x i32> *%a2, align 16 %2 = load <4 x i32>, <4 x i32> *%a2, align 16
%3 = add <4 x i32> %1, %2 %3 = add <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <2 x i64> @test_paddq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_paddq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_paddq: ; GENERIC-LABEL: test_paddq:
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; HASWELL-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddq: ; BTVER2-LABEL: test_paddq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddq: ; ZNVER1-LABEL: test_paddq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = add <2 x i64> %a0, %a1 %1 = add <2 x i64> %a0, %a1
%2 = load <2 x i64>, <2 x i64> *%a2, align 16 %2 = load <2 x i64>, <2 x i64> *%a2, align 16
%3 = add <2 x i64> %1, %2 %3 = add <2 x i64> %1, %2
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <16 x i8> @test_paddsb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_paddsb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
; GENERIC-LABEL: test_paddsb: ; GENERIC-LABEL: test_paddsb:
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; HASWELL-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddsb: ; BTVER2-LABEL: test_paddsb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddsb: ; ZNVER1-LABEL: test_paddsb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %a0, <16 x i8> %a1) %1 = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %a0, <16 x i8> %a1)
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %1, <16 x i8> %2) %3 = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %1, <16 x i8> %2)
ret <16 x i8> %3 ret <16 x i8> %3
} }
declare <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8>, <16 x i8>) nounwind readnone
define <8 x i16> @test_paddsw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_paddsw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddsw: ; BTVER2-LABEL: test_paddsw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddsw: ; ZNVER1-LABEL: test_paddsw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone
define <16 x i8> @test_paddusb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_paddusb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
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; HASWELL-LABEL: test_paddusb: ; HASWELL-LABEL: test_paddusb:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddusb: ; BTVER2-LABEL: test_paddusb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddusb: ; ZNVER1-LABEL: test_paddusb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %a0, <16 x i8> %a1) %1 = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %a0, <16 x i8> %a1)
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %1, <16 x i8> %2) %3 = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %1, <16 x i8> %2)
ret <16 x i8> %3 ret <16 x i8> %3
} }
declare <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8>, <16 x i8>) nounwind readnone
define <8 x i16> @test_paddusw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_paddusw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; ;
; HASWELL-LABEL: test_paddusw: ; HASWELL-LABEL: test_paddusw:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddusw: ; BTVER2-LABEL: test_paddusw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddusw: ; ZNVER1-LABEL: test_paddusw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.paddus.w(<8 x i16>, <8 x i16>) nounwind readnone
define <8 x i16> @test_paddw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_paddw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; HASWELL-LABEL: test_paddw: ; HASWELL-LABEL: test_paddw:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_paddw: ; BTVER2-LABEL: test_paddw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_paddw: ; ZNVER1-LABEL: test_paddw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = add <8 x i16> %a0, %a1 %1 = add <8 x i16> %a0, %a1
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = add <8 x i16> %1, %2 %3 = add <8 x i16> %1, %2
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <2 x i64> @test_pand(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_pand(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_pand: ; GENERIC-LABEL: test_pand:
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; BTVER2-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pand: ; ZNVER1-LABEL: test_pand:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = and <2 x i64> %a0, %a1 %1 = and <2 x i64> %a0, %a1
%2 = load <2 x i64>, <2 x i64> *%a2, align 16 %2 = load <2 x i64>, <2 x i64> *%a2, align 16
%3 = and <2 x i64> %1, %2 %3 = and <2 x i64> %1, %2
%4 = add <2 x i64> %3, %a1 %4 = add <2 x i64> %3, %a1
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @test_pandn(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_pandn(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
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; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.33] ; HASWELL-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [5:0.50] ; HASWELL-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [5:0.50]
; HASWELL-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pandn: ; BTVER2-LABEL: test_pandn:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [6:1.00] ; BTVER2-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [6:1.00]
; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pandn: ; ZNVER1-LABEL: test_pandn:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [8:0.50] ; ZNVER1-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [8:0.50]
; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = xor <2 x i64> %a0, <i64 -1, i64 -1> %1 = xor <2 x i64> %a0, <i64 -1, i64 -1>
%2 = and <2 x i64> %a1, %1 %2 = and <2 x i64> %a1, %1
%3 = load <2 x i64>, <2 x i64> *%a2, align 16 %3 = load <2 x i64>, <2 x i64> *%a2, align 16
%4 = xor <2 x i64> %2, <i64 -1, i64 -1> %4 = xor <2 x i64> %2, <i64 -1, i64 -1>
%5 = and <2 x i64> %3, %4 %5 = and <2 x i64> %3, %4
%6 = add <2 x i64> %2, %5 %6 = add <2 x i64> %2, %5
ret <2 x i64> %6 ret <2 x i64> %6
} }
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; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [7:0.50] ; SANDY-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pavgb: ; HASWELL-LABEL: test_pavgb:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pavgb: ; BTVER2-LABEL: test_pavgb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pavgb: ; ZNVER1-LABEL: test_pavgb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) %1 = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1)
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %1, <16 x i8> %2) %3 = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %1, <16 x i8> %2)
ret <16 x i8> %3 ret <16 x i8> %3
} }
declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %arg0, <16 x i8> %arg1) nounwind readnone declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %arg0, <16 x i8> %arg1) nounwind readnone
define <8 x i16> @test_pavgw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_pavgw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; ;
; HASWELL-LABEL: test_pavgw: ; HASWELL-LABEL: test_pavgw:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pavgw: ; BTVER2-LABEL: test_pavgw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pavgw: ; ZNVER1-LABEL: test_pavgw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
define <16 x i8> @test_pcmpeqb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_pcmpeqb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
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; HASWELL-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; HASWELL-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; HASWELL-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33] ; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pcmpeqb: ; BTVER2-LABEL: test_pcmpeqb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; BTVER2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; BTVER2-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pcmpeqb: ; ZNVER1-LABEL: test_pcmpeqb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = icmp eq <16 x i8> %a0, %a1 %1 = icmp eq <16 x i8> %a0, %a1
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = icmp eq <16 x i8> %a0, %2 %3 = icmp eq <16 x i8> %a0, %2
%4 = or <16 x i1> %1, %3 %4 = or <16 x i1> %1, %3
%5 = sext <16 x i1> %4 to <16 x i8> %5 = sext <16 x i1> %4 to <16 x i8>
ret <16 x i8> %5 ret <16 x i8> %5
} }
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; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; HASWELL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; HASWELL-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33] ; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pcmpeqd: ; BTVER2-LABEL: test_pcmpeqd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; BTVER2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; BTVER2-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pcmpeqd: ; ZNVER1-LABEL: test_pcmpeqd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = icmp eq <4 x i32> %a0, %a1 %1 = icmp eq <4 x i32> %a0, %a1
%2 = load <4 x i32>, <4 x i32> *%a2, align 16 %2 = load <4 x i32>, <4 x i32> *%a2, align 16
%3 = icmp eq <4 x i32> %a0, %2 %3 = icmp eq <4 x i32> %a0, %2
%4 = or <4 x i1> %1, %3 %4 = or <4 x i1> %1, %3
%5 = sext <4 x i1> %4 to <4 x i32> %5 = sext <4 x i1> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }
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; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; HASWELL-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; HASWELL-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33] ; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pcmpeqw: ; BTVER2-LABEL: test_pcmpeqw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; BTVER2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; BTVER2-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pcmpeqw: ; ZNVER1-LABEL: test_pcmpeqw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = icmp eq <8 x i16> %a0, %a1 %1 = icmp eq <8 x i16> %a0, %a1
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = icmp eq <8 x i16> %a0, %2 %3 = icmp eq <8 x i16> %a0, %2
%4 = or <8 x i1> %1, %3 %4 = or <8 x i1> %1, %3
%5 = sext <8 x i1> %4 to <8 x i16> %5 = sext <8 x i1> %4 to <8 x i16>
ret <8 x i16> %5 ret <8 x i16> %5
} }
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; HASWELL-LABEL: test_pcmpgtb: ; HASWELL-LABEL: test_pcmpgtb:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; HASWELL-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; HASWELL-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33] ; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pcmpgtb: ; BTVER2-LABEL: test_pcmpgtb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; BTVER2-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; BTVER2-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pcmpgtb: ; ZNVER1-LABEL: test_pcmpgtb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = icmp sgt <16 x i8> %a0, %a1 %1 = icmp sgt <16 x i8> %a0, %a1
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = icmp sgt <16 x i8> %a0, %2 %3 = icmp sgt <16 x i8> %a0, %2
%4 = or <16 x i1> %1, %3 %4 = or <16 x i1> %1, %3
%5 = sext <16 x i1> %4 to <16 x i8> %5 = sext <16 x i1> %4 to <16 x i8>
ret <16 x i8> %5 ret <16 x i8> %5
} }
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; ;
; HASWELL-LABEL: test_pcmpgtd: ; HASWELL-LABEL: test_pcmpgtd:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; HASWELL-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; HASWELL-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33] ; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pcmpgtd: ; BTVER2-LABEL: test_pcmpgtd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; BTVER2-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; BTVER2-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pcmpgtd: ; ZNVER1-LABEL: test_pcmpgtd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = icmp sgt <4 x i32> %a0, %a1 %1 = icmp sgt <4 x i32> %a0, %a1
%2 = load <4 x i32>, <4 x i32> *%a2, align 16 %2 = load <4 x i32>, <4 x i32> *%a2, align 16
%3 = icmp eq <4 x i32> %a0, %2 %3 = icmp eq <4 x i32> %a0, %2
%4 = or <4 x i1> %1, %3 %4 = or <4 x i1> %1, %3
%5 = sext <4 x i1> %4 to <4 x i32> %5 = sext <4 x i1> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }
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; SLM-NEXT: pcmpgtw (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: pcmpgtw (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: pcmpgtw %xmm1, %xmm2 # sched: [1:0.50] ; SLM-NEXT: pcmpgtw %xmm1, %xmm2 # sched: [1:0.50]
; SLM-NEXT: por %xmm2, %xmm0 # sched: [1:0.50] ; SLM-NEXT: por %xmm2, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pcmpgtw: ; SANDY-LABEL: test_pcmpgtw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; SANDY-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; SANDY-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [7:0.50] ; SANDY-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SANDY-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33] ; SANDY-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pcmpgtw: ; HASWELL-LABEL: test_pcmpgtw:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; HASWELL-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; HASWELL-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33] ; HASWELL-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pcmpgtw: ; BTVER2-LABEL: test_pcmpgtw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50] ; BTVER2-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
; BTVER2-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pcmpgtw: ; ZNVER1-LABEL: test_pcmpgtw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.25]
; ZNVER1-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = icmp sgt <8 x i16> %a0, %a1 %1 = icmp sgt <8 x i16> %a0, %a1
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = icmp sgt <8 x i16> %a0, %2 %3 = icmp sgt <8 x i16> %a0, %2
%4 = or <8 x i1> %1, %3 %4 = or <8 x i1> %1, %3
%5 = sext <8 x i1> %4 to <8 x i16> %5 = sext <8 x i1> %4 to <8 x i16>
ret <8 x i16> %5 ret <8 x i16> %5
} }
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; ATOM-NEXT: pextrw $6, %xmm0, %eax # sched: [4:2.00] ; ATOM-NEXT: pextrw $6, %xmm0, %eax # sched: [4:2.00]
; ATOM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; ATOM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pextrw: ; SLM-LABEL: test_pextrw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pextrw $6, %xmm0, %eax # sched: [4:1.00] ; SLM-NEXT: pextrw $6, %xmm0, %eax # sched: [4:1.00]
; SLM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; SLM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pextrw: ; SANDY-LABEL: test_pextrw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpextrw $6, %xmm0, %eax # sched: [3:1.00] ; SANDY-NEXT: vpextrw $6, %xmm0, %eax # sched: [3:1.00]
; SANDY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; SANDY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pextrw: ; HASWELL-LABEL: test_pextrw:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:1.00] ; HASWELL-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:1.00]
; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pextrw: ; BTVER2-LABEL: test_pextrw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:0.50] ; BTVER2-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:0.50]
; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pextrw: ; ZNVER1-LABEL: test_pextrw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:0.25] ; ZNVER1-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:0.25]
; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = extractelement <8 x i16> %a0, i32 6 %1 = extractelement <8 x i16> %a0, i32 6
ret i16 %1 ret i16 %1
} }
define <8 x i16> @test_pinsrw(<8 x i16> %a0, i16 %a1, i16 *%a2) { define <8 x i16> @test_pinsrw(<8 x i16> %a0, i16 %a1, i16 *%a2) {
; GENERIC-LABEL: test_pinsrw: ; GENERIC-LABEL: test_pinsrw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pinsrw $1, %edi, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: pinsrw $1, %edi, %xmm0 # sched: [2:1.00]
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; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pinsrw $1, %edi, %xmm0 # sched: [1:1.00] ; SLM-NEXT: pinsrw $1, %edi, %xmm0 # sched: [1:1.00]
; SLM-NEXT: pinsrw $3, (%rsi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: pinsrw $3, (%rsi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pinsrw: ; SANDY-LABEL: test_pinsrw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [2:1.00] ; SANDY-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [2:1.00]
; SANDY-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [7:0.50] ; SANDY-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [7:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pinsrw: ; HASWELL-LABEL: test_pinsrw:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:1.00] ; HASWELL-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:1.00]
; HASWELL-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [5:1.00] ; HASWELL-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [5:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pinsrw: ; BTVER2-LABEL: test_pinsrw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pinsrw: ; ZNVER1-LABEL: test_pinsrw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = insertelement <8 x i16> %a0, i16 %a1, i32 1 %1 = insertelement <8 x i16> %a0, i16 %a1, i32 1
%2 = load i16, i16 *%a2 %2 = load i16, i16 *%a2
%3 = insertelement <8 x i16> %1, i16 %2, i32 3 %3 = insertelement <8 x i16> %1, i16 %2, i32 3
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <4 x i32> @test_pmaddwd(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <4 x i32> @test_pmaddwd(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_pmaddwd: ; GENERIC-LABEL: test_pmaddwd:
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; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pmaddwd: ; SLM-LABEL: test_pmaddwd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pmaddwd %xmm1, %xmm0 # sched: [4:1.00] ; SLM-NEXT: pmaddwd %xmm1, %xmm0 # sched: [4:1.00]
; SLM-NEXT: pmaddwd (%rdi), %xmm0 # sched: [7:1.00] ; SLM-NEXT: pmaddwd (%rdi), %xmm0 # sched: [7:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pmaddwd: ; SANDY-LABEL: test_pmaddwd:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SANDY-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [9:1.00] ; SANDY-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pmaddwd: ; HASWELL-LABEL: test_pmaddwd:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [5:1.00] ; HASWELL-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
; HASWELL-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [9:1.00] ; HASWELL-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pmaddwd: ; BTVER2-LABEL: test_pmaddwd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmaddwd: ; ZNVER1-LABEL: test_pmaddwd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [4:1.00] ; ZNVER1-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [11:1.00] ; ZNVER1-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) %1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1)
%2 = bitcast <4 x i32> %1 to <8 x i16> %2 = bitcast <4 x i32> %1 to <8 x i16>
%3 = load <8 x i16>, <8 x i16> *%a2, align 16 %3 = load <8 x i16>, <8 x i16> *%a2, align 16
%4 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %2, <8 x i16> %3) %4 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %2, <8 x i16> %3)
ret <4 x i32> %4 ret <4 x i32> %4
} }
declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
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; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pmaxsw: ; SLM-LABEL: test_pmaxsw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pmaxsw %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: pmaxsw %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: pmaxsw (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: pmaxsw (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pmaxsw: ; SANDY-LABEL: test_pmaxsw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50] ; SANDY-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pmaxsw: ; HASWELL-LABEL: test_pmaxsw:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pmaxsw: ; BTVER2-LABEL: test_pmaxsw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmaxsw: ; ZNVER1-LABEL: test_pmaxsw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone
define <16 x i8> @test_pmaxub(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_pmaxub(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
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; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pmaxub: ; SLM-LABEL: test_pmaxub:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pmaxub %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: pmaxub %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: pmaxub (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: pmaxub (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pmaxub: ; SANDY-LABEL: test_pmaxub:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [7:0.50] ; SANDY-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
; ;
; HASWELL-LABEL: test_pmaxub: ; HASWELL-LABEL: test_pmaxub:
; HASWELL: # BB#0: ; HASWELL: # BB#0:
; HASWELL-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; HASWELL-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; HASWELL-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [5:0.50] ; HASWELL-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [5:0.50]
; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_pmaxub: ; BTVER2-LABEL: test_pmaxub:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmaxub: ; ZNVER1-LABEL: test_pmaxub:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1) %1 = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1)
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %1, <16 x i8> %2) %3 = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %1, <16 x i8> %2)
ret <16 x i8> %3 ret <16 x i8> %3
} }
declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone
define <8 x i16> @test_pminsw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_pminsw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pminsw: ; SLM-LABEL: test_pminsw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pminsw %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: pminsw %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: pminsw (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: pminsw (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pminsw: ; SANDY-LABEL: test_pminsw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50] ; SANDY-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
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; BTVER2-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pminsw: ; ZNVER1-LABEL: test_pminsw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone
define <16 x i8> @test_pminub(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_pminub(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
; GENERIC-LABEL: test_pminub: ; GENERIC-LABEL: test_pminub:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pminub %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: pminub %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: pminub (%rdi), %xmm0 # sched: [7:0.50] ; GENERIC-NEXT: pminub (%rdi), %xmm0 # sched: [7:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pminub: ; ATOM-LABEL: test_pminub:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pminub %xmm1, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: pminub %xmm1, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: pminub (%rdi), %xmm0 # sched: [1:1.00] ; ATOM-NEXT: pminub (%rdi), %xmm0 # sched: [1:1.00]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pminub: ; SLM-LABEL: test_pminub:
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; BTVER2-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pminub: ; ZNVER1-LABEL: test_pminub:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1) %1 = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1)
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %1, <16 x i8> %2) %3 = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %1, <16 x i8> %2)
ret <16 x i8> %3 ret <16 x i8> %3
} }
declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone
define i32 @test_pmovmskb(<16 x i8> %a0) { define i32 @test_pmovmskb(<16 x i8> %a0) {
; GENERIC-LABEL: test_pmovmskb: ; GENERIC-LABEL: test_pmovmskb:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pmovmskb %xmm0, %eax # sched: [2:1.00] ; GENERIC-NEXT: pmovmskb %xmm0, %eax # sched: [2:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pmovmskb: ; ATOM-LABEL: test_pmovmskb:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pmovmskb %xmm0, %eax # sched: [3:3.00] ; ATOM-NEXT: pmovmskb %xmm0, %eax # sched: [3:3.00]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
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; ;
; BTVER2-LABEL: test_pmovmskb: ; BTVER2-LABEL: test_pmovmskb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpmovmskb %xmm0, %eax # sched: [1:0.50] ; BTVER2-NEXT: vpmovmskb %xmm0, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmovmskb: ; ZNVER1-LABEL: test_pmovmskb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmovmskb %xmm0, %eax # sched: [1:0.25] ; ZNVER1-NEXT: vpmovmskb %xmm0, %eax # sched: [1:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) %1 = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0)
ret i32 %1 ret i32 %1
} }
declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone
define <8 x i16> @test_pmulhuw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_pmulhuw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_pmulhuw: ; GENERIC-LABEL: test_pmulhuw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pmulhuw %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: pmulhuw %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: pmulhuw (%rdi), %xmm0 # sched: [9:1.00] ; GENERIC-NEXT: pmulhuw (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pmulhuw: ; ATOM-LABEL: test_pmulhuw:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pmulhuw %xmm1, %xmm0 # sched: [5:5.00] ; ATOM-NEXT: pmulhuw %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: pmulhuw (%rdi), %xmm0 # sched: [5:5.00] ; ATOM-NEXT: pmulhuw (%rdi), %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pmulhuw: ; SLM-LABEL: test_pmulhuw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pmulhuw %xmm1, %xmm0 # sched: [4:1.00] ; SLM-NEXT: pmulhuw %xmm1, %xmm0 # sched: [4:1.00]
; SLM-NEXT: pmulhuw (%rdi), %xmm0 # sched: [7:1.00] ; SLM-NEXT: pmulhuw (%rdi), %xmm0 # sched: [7:1.00]
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; BTVER2-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmulhuw: ; ZNVER1-LABEL: test_pmulhuw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [4:1.00] ; ZNVER1-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [11:1.00] ; ZNVER1-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
define <8 x i16> @test_pmulhw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_pmulhw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_pmulhw: ; GENERIC-LABEL: test_pmulhw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pmulhw %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: pmulhw %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: pmulhw (%rdi), %xmm0 # sched: [9:1.00] ; GENERIC-NEXT: pmulhw (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pmulhw: ; ATOM-LABEL: test_pmulhw:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pmulhw %xmm1, %xmm0 # sched: [5:5.00] ; ATOM-NEXT: pmulhw %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: pmulhw (%rdi), %xmm0 # sched: [5:5.00] ; ATOM-NEXT: pmulhw (%rdi), %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pmulhw: ; SLM-LABEL: test_pmulhw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pmulhw %xmm1, %xmm0 # sched: [4:1.00] ; SLM-NEXT: pmulhw %xmm1, %xmm0 # sched: [4:1.00]
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; BTVER2-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmulhw: ; ZNVER1-LABEL: test_pmulhw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [4:1.00] ; ZNVER1-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [11:1.00] ; ZNVER1-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
define <8 x i16> @test_pmullw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_pmullw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_pmullw: ; GENERIC-LABEL: test_pmullw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pmullw %xmm1, %xmm0 # sched: [3:1.00] ; GENERIC-NEXT: pmullw %xmm1, %xmm0 # sched: [3:1.00]
; GENERIC-NEXT: pmullw (%rdi), %xmm0 # sched: [9:1.00] ; GENERIC-NEXT: pmullw (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pmullw: ; ATOM-LABEL: test_pmullw:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pmullw %xmm1, %xmm0 # sched: [5:5.00] ; ATOM-NEXT: pmullw %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: pmullw (%rdi), %xmm0 # sched: [5:5.00] ; ATOM-NEXT: pmullw (%rdi), %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pmullw: ; SLM-LABEL: test_pmullw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pmullw %xmm1, %xmm0 # sched: [4:1.00] ; SLM-NEXT: pmullw %xmm1, %xmm0 # sched: [4:1.00]
; SLM-NEXT: pmullw (%rdi), %xmm0 # sched: [7:1.00] ; SLM-NEXT: pmullw (%rdi), %xmm0 # sched: [7:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pmullw: ; SANDY-LABEL: test_pmullw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
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; BTVER2-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmullw: ; ZNVER1-LABEL: test_pmullw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [4:1.00] ; ZNVER1-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [11:1.00] ; ZNVER1-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = mul <8 x i16> %a0, %a1 %1 = mul <8 x i16> %a0, %a1
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = mul <8 x i16> %1, %2 %3 = mul <8 x i16> %1, %2
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <2 x i64> @test_pmuludq(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { define <2 x i64> @test_pmuludq(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
; GENERIC-LABEL: test_pmuludq: ; GENERIC-LABEL: test_pmuludq:
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; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pmuludq: ; SLM-LABEL: test_pmuludq:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pmuludq %xmm1, %xmm0 # sched: [4:1.00] ; SLM-NEXT: pmuludq %xmm1, %xmm0 # sched: [4:1.00]
; SLM-NEXT: pmuludq (%rdi), %xmm0 # sched: [7:1.00] ; SLM-NEXT: pmuludq (%rdi), %xmm0 # sched: [7:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pmuludq: ; SANDY-LABEL: test_pmuludq:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
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; BTVER2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pmuludq: ; ZNVER1-LABEL: test_pmuludq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [4:1.00] ; ZNVER1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [11:1.00] ; ZNVER1-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1) %1 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1)
%2 = bitcast <2 x i64> %1 to <4 x i32> %2 = bitcast <2 x i64> %1 to <4 x i32>
%3 = load <4 x i32>, <4 x i32> *%a2, align 16 %3 = load <4 x i32>, <4 x i32> *%a2, align 16
%4 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %2, <4 x i32> %3) %4 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %2, <4 x i32> %3)
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone
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; ATOM-NEXT: por (%rdi), %xmm0 # sched: [1:1.00] ; ATOM-NEXT: por (%rdi), %xmm0 # sched: [1:1.00]
; ATOM-NEXT: paddq %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: paddq %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_por: ; SLM-LABEL: test_por:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: por %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: por %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: por (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: por (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: paddq %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: paddq %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_por: ; SANDY-LABEL: test_por:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33] ; SANDY-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SANDY-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [7:0.50] ; SANDY-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SANDY-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; SANDY-NEXT: retq # sched: [1:1.00] ; SANDY-NEXT: retq # sched: [1:1.00]
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; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_por: ; ZNVER1-LABEL: test_por:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = or <2 x i64> %a0, %a1 %1 = or <2 x i64> %a0, %a1
%2 = load <2 x i64>, <2 x i64> *%a2, align 16 %2 = load <2 x i64>, <2 x i64> *%a2, align 16
%3 = or <2 x i64> %1, %2 %3 = or <2 x i64> %1, %2
%4 = add <2 x i64> %3, %a1 %4 = add <2 x i64> %3, %a1
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @test_psadbw(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <2 x i64> @test_psadbw(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
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; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_psadbw: ; SLM-LABEL: test_psadbw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: psadbw %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: psadbw %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: psadbw (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: psadbw (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_psadbw: ; SANDY-LABEL: test_psadbw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; SANDY-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
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; BTVER2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [7:1.00] ; BTVER2-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psadbw: ; ZNVER1-LABEL: test_psadbw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [4:1.00] ; ZNVER1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
; ZNVER1-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [11:1.00] ; ZNVER1-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) %1 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1)
%2 = bitcast <2 x i64> %1 to <16 x i8> %2 = bitcast <2 x i64> %1 to <16 x i8>
%3 = load <16 x i8>, <16 x i8> *%a2, align 16 %3 = load <16 x i8>, <16 x i8> *%a2, align 16
%4 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %2, <16 x i8> %3) %4 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %2, <16 x i8> %3)
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
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; ATOM-NEXT: paddd %xmm0, %xmm1 # sched: [1:0.50] ; ATOM-NEXT: paddd %xmm0, %xmm1 # sched: [1:0.50]
; ATOM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pshufd: ; SLM-LABEL: test_pshufd:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [4:1.00] ; SLM-NEXT: pshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [4:1.00]
; SLM-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:1.00] ; SLM-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:1.00]
; SLM-NEXT: paddd %xmm0, %xmm1 # sched: [1:0.50] ; SLM-NEXT: paddd %xmm0, %xmm1 # sched: [1:0.50]
; SLM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pshufd: ; SANDY-LABEL: test_pshufd:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:0.50] ; SANDY-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:0.50]
; SANDY-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [7:0.50] ; SANDY-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [7:0.50]
; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; SANDY-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
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; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pshufd: ; ZNVER1-LABEL: test_pshufd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [8:0.50] ; ZNVER1-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [8:0.50]
; ZNVER1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:0.25] ; ZNVER1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:0.25]
; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
%2 = load <4 x i32>, <4 x i32> *%a1, align 16 %2 = load <4 x i32>, <4 x i32> *%a1, align 16
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%4 = add <4 x i32> %1, %3 %4 = add <4 x i32> %1, %3
ret <4 x i32> %4 ret <4 x i32> %4
} }
define <8 x i16> @test_pshufhw(<8 x i16> %a0, <8 x i16> *%a1) { define <8 x i16> @test_pshufhw(<8 x i16> %a0, <8 x i16> *%a1) {
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; ATOM-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:1.00] ; ATOM-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:1.00]
; ATOM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50] ; ATOM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50]
; ATOM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pshufhw: ; SLM-LABEL: test_pshufhw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [4:1.00] ; SLM-NEXT: pshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [4:1.00]
; SLM-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:1.00] ; SLM-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:1.00]
; SLM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50] ; SLM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50]
; SLM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pshufhw: ; SANDY-LABEL: test_pshufhw:
; SANDY: # BB#0: ; SANDY: # BB#0:
; SANDY-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:0.50] ; SANDY-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:0.50]
; SANDY-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [7:0.50] ; SANDY-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [7:0.50]
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; BTVER2-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pshufhw: ; ZNVER1-LABEL: test_pshufhw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [8:0.50] ; ZNVER1-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [8:0.50]
; ZNVER1-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:0.25] ; ZNVER1-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:0.25]
; ZNVER1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 7, i32 6> %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 7, i32 6>
%2 = load <8 x i16>, <8 x i16> *%a1, align 16 %2 = load <8 x i16>, <8 x i16> *%a1, align 16
%3 = shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 5, i32 4> %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 5, i32 4>
%4 = add <8 x i16> %1, %3 %4 = add <8 x i16> %1, %3
ret <8 x i16> %4 ret <8 x i16> %4
} }
define <8 x i16> @test_pshuflw(<8 x i16> %a0, <8 x i16> *%a1) { define <8 x i16> @test_pshuflw(<8 x i16> %a0, <8 x i16> *%a1) {
; GENERIC-LABEL: test_pshuflw: ; GENERIC-LABEL: test_pshuflw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[1,0,3,2,4,5,6,7] sched: [1:0.50] ; GENERIC-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[1,0,3,2,4,5,6,7] sched: [1:0.50]
; GENERIC-NEXT: pshuflw {{.*#+}} xmm0 = mem[3,2,1,0,4,5,6,7] sched: [7:0.50] ; GENERIC-NEXT: pshuflw {{.*#+}} xmm0 = mem[3,2,1,0,4,5,6,7] sched: [7:0.50]
; GENERIC-NEXT: paddw %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: paddw %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pshuflw: ; ATOM-LABEL: test_pshuflw:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [1:1.00] ; ATOM-NEXT: pshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [1:1.00]
; ATOM-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:1.00] ; ATOM-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:1.00]
; ATOM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50] ; ATOM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50]
; ATOM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pshuflw: ; SLM-LABEL: test_pshuflw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: pshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [4:1.00] ; SLM-NEXT: pshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [4:1.00]
; SLM-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:1.00] ; SLM-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:1.00]
; SLM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50] ; SLM-NEXT: paddw %xmm0, %xmm1 # sched: [1:0.50]
; SLM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50] ; SLM-NEXT: movdqa %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_pshuflw: ; SANDY-LABEL: test_pshuflw:
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; BTVER2-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pshuflw: ; ZNVER1-LABEL: test_pshuflw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [8:0.50] ; ZNVER1-NEXT: vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [8:0.50]
; ZNVER1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:0.25] ; ZNVER1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:0.25]
; ZNVER1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7> %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7>
%2 = load <8 x i16>, <8 x i16> *%a1, align 16 %2 = load <8 x i16>, <8 x i16> *%a1, align 16
%3 = shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
%4 = add <8 x i16> %1, %3 %4 = add <8 x i16> %1, %3
ret <8 x i16> %4 ret <8 x i16> %4
} }
define <4 x i32> @test_pslld(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { define <4 x i32> @test_pslld(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
; GENERIC-LABEL: test_pslld: ; GENERIC-LABEL: test_pslld:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pslld %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: pslld %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: pslld (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: pslld (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: pslld $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: pslld $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pslld: ; ATOM-LABEL: test_pslld:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pslld %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: pslld %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: pslld (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: pslld (%rdi), %xmm0 # sched: [3:1.50]
; ATOM-NEXT: pslld $2, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: pslld $2, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_pslld: ; SLM-LABEL: test_pslld:
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pslld: ; ZNVER1-LABEL: test_pslld:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) %1 = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1)
%2 = load <4 x i32>, <4 x i32> *%a2, align 16 %2 = load <4 x i32>, <4 x i32> *%a2, align 16
%3 = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %1, <4 x i32> %2) %3 = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %1, <4 x i32> %2)
%4 = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %3, i32 2) %4 = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %3, i32 2)
ret <4 x i32> %4 ret <4 x i32> %4
} }
declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone
define <4 x i32> @test_pslldq(<4 x i32> %a0) { define <4 x i32> @test_pslldq(<4 x i32> %a0) {
; GENERIC-LABEL: test_pslldq: ; GENERIC-LABEL: test_pslldq:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:0.50] ; GENERIC-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_pslldq: ; ATOM-LABEL: test_pslldq:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:0.50] ; ATOM-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:0.50]
; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50]
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; ;
; BTVER2-LABEL: test_pslldq: ; BTVER2-LABEL: test_pslldq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:0.50] ; BTVER2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_pslldq: ; ZNVER1-LABEL: test_pslldq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:0.25] ; ZNVER1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 1, i32 2> %1 = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <2 x i64> @test_psllq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_psllq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_psllq: ; GENERIC-LABEL: test_psllq:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psllq %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: psllq %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: psllq (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: psllq (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: psllq $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: psllq $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_psllq: ; ATOM-LABEL: test_psllq:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: psllq %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: psllq %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: psllq (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: psllq (%rdi), %xmm0 # sched: [3:1.50]
; ATOM-NEXT: psllq $2, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: psllq $2, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_psllq: ; SLM-LABEL: test_psllq:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: psllq %xmm1, %xmm0 # sched: [1:1.00] ; SLM-NEXT: psllq %xmm1, %xmm0 # sched: [1:1.00]
; SLM-NEXT: psllq (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: psllq (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: psllq $2, %xmm0 # sched: [1:1.00] ; SLM-NEXT: psllq $2, %xmm0 # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psllq: ; ZNVER1-LABEL: test_psllq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) %1 = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1)
%2 = load <2 x i64>, <2 x i64> *%a2, align 16 %2 = load <2 x i64>, <2 x i64> *%a2, align 16
%3 = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %1, <2 x i64> %2) %3 = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %1, <2 x i64> %2)
%4 = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %3, i32 2) %4 = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %3, i32 2)
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
define <8 x i16> @test_psllw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_psllw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_psllw: ; GENERIC-LABEL: test_psllw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psllw %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: psllw %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: psllw (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: psllw (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: psllw $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: psllw $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_psllw: ; ATOM-LABEL: test_psllw:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: psllw %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: psllw %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: psllw (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: psllw (%rdi), %xmm0 # sched: [3:1.50]
; ATOM-NEXT: psllw $2, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: psllw $2, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_psllw: ; SLM-LABEL: test_psllw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: psllw %xmm1, %xmm0 # sched: [1:1.00] ; SLM-NEXT: psllw %xmm1, %xmm0 # sched: [1:1.00]
; SLM-NEXT: psllw (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: psllw (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: psllw $2, %xmm0 # sched: [1:1.00] ; SLM-NEXT: psllw $2, %xmm0 # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psllw: ; ZNVER1-LABEL: test_psllw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %1, <8 x i16> %2)
%4 = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %3, i32 2) %4 = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %3, i32 2)
ret <8 x i16> %4 ret <8 x i16> %4
} }
declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone
define <4 x i32> @test_psrad(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { define <4 x i32> @test_psrad(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
; GENERIC-LABEL: test_psrad: ; GENERIC-LABEL: test_psrad:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psrad %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: psrad %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: psrad (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: psrad (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: psrad $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: psrad $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_psrad: ; ATOM-LABEL: test_psrad:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: psrad %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: psrad %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: psrad (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: psrad (%rdi), %xmm0 # sched: [3:1.50]
; ATOM-NEXT: psrad $2, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: psrad $2, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_psrad: ; SLM-LABEL: test_psrad:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: psrad %xmm1, %xmm0 # sched: [1:1.00] ; SLM-NEXT: psrad %xmm1, %xmm0 # sched: [1:1.00]
; SLM-NEXT: psrad (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: psrad (%rdi), %xmm0 # sched: [4:1.00]
; SLM-NEXT: psrad $2, %xmm0 # sched: [1:1.00] ; SLM-NEXT: psrad $2, %xmm0 # sched: [1:1.00]
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psrad: ; ZNVER1-LABEL: test_psrad:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) %1 = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1)
%2 = load <4 x i32>, <4 x i32> *%a2, align 16 %2 = load <4 x i32>, <4 x i32> *%a2, align 16
%3 = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %1, <4 x i32> %2) %3 = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %1, <4 x i32> %2)
%4 = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %3, i32 2) %4 = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %3, i32 2)
ret <4 x i32> %4 ret <4 x i32> %4
} }
declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone
declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone
define <8 x i16> @test_psraw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_psraw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_psraw: ; GENERIC-LABEL: test_psraw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psraw %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: psraw %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: psraw (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: psraw (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: psraw $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: psraw $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_psraw: ; ATOM-LABEL: test_psraw:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: psraw %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: psraw %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: psraw (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: psraw (%rdi), %xmm0 # sched: [3:1.50]
; ATOM-NEXT: psraw $2, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: psraw $2, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_psraw: ; SLM-LABEL: test_psraw:
; SLM: # BB#0: ; SLM: # BB#0:
; SLM-NEXT: psraw %xmm1, %xmm0 # sched: [1:1.00] ; SLM-NEXT: psraw %xmm1, %xmm0 # sched: [1:1.00]
; SLM-NEXT: psraw (%rdi), %xmm0 # sched: [4:1.00] ; SLM-NEXT: psraw (%rdi), %xmm0 # sched: [4:1.00]
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psraw: ; ZNVER1-LABEL: test_psraw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %1, <8 x i16> %2)
%4 = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %3, i32 2) %4 = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %3, i32 2)
ret <8 x i16> %4 ret <8 x i16> %4
} }
declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
define <4 x i32> @test_psrld(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { define <4 x i32> @test_psrld(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
; GENERIC-LABEL: test_psrld: ; GENERIC-LABEL: test_psrld:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psrld %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: psrld %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: psrld (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: psrld (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: psrld $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: psrld $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_psrld: ; ATOM-LABEL: test_psrld:
; ATOM: # BB#0: ; ATOM: # BB#0:
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psrld: ; ZNVER1-LABEL: test_psrld:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) %1 = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1)
%2 = load <4 x i32>, <4 x i32> *%a2, align 16 %2 = load <4 x i32>, <4 x i32> *%a2, align 16
%3 = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %1, <4 x i32> %2) %3 = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %1, <4 x i32> %2)
%4 = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %3, i32 2) %4 = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %3, i32 2)
ret <4 x i32> %4 ret <4 x i32> %4
} }
declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone
declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone
define <4 x i32> @test_psrldq(<4 x i32> %a0) { define <4 x i32> @test_psrldq(<4 x i32> %a0) {
; GENERIC-LABEL: test_psrldq: ; GENERIC-LABEL: test_psrldq:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:0.50] ; GENERIC-NEXT: psrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:0.50]
Show All 27 Lines
; ;
; BTVER2-LABEL: test_psrldq: ; BTVER2-LABEL: test_psrldq:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:0.50] ; BTVER2-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psrldq: ; ZNVER1-LABEL: test_psrldq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:0.25] ; ZNVER1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:1.00]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 4> %1 = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <2 x i64> @test_psrlq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_psrlq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_psrlq: ; GENERIC-LABEL: test_psrlq:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psrlq %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: psrlq %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: psrlq (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: psrlq (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: psrlq $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: psrlq $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_psrlq: ; ATOM-LABEL: test_psrlq:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: psrlq %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: psrlq %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: psrlq (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: psrlq (%rdi), %xmm0 # sched: [3:1.50]
; ATOM-NEXT: psrlq $2, %xmm0 # sched: [1:0.50] ; ATOM-NEXT: psrlq $2, %xmm0 # sched: [1:0.50]
; ATOM-NEXT: retq # sched: [79:39.50] ; ATOM-NEXT: retq # sched: [79:39.50]
; ;
; SLM-LABEL: test_psrlq: ; SLM-LABEL: test_psrlq:
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psrlq: ; ZNVER1-LABEL: test_psrlq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) %1 = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1)
%2 = load <2 x i64>, <2 x i64> *%a2, align 16 %2 = load <2 x i64>, <2 x i64> *%a2, align 16
%3 = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %1, <2 x i64> %2) %3 = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %1, <2 x i64> %2)
%4 = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %3, i32 2) %4 = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %3, i32 2)
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone
define <8 x i16> @test_psrlw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_psrlw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_psrlw: ; GENERIC-LABEL: test_psrlw:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psrlw %xmm1, %xmm0 # sched: [2:1.00] ; GENERIC-NEXT: psrlw %xmm1, %xmm0 # sched: [2:1.00]
; GENERIC-NEXT: psrlw (%rdi), %xmm0 # sched: [8:1.00] ; GENERIC-NEXT: psrlw (%rdi), %xmm0 # sched: [8:1.00]
; GENERIC-NEXT: psrlw $2, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: psrlw $2, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00] ; GENERIC-NEXT: retq # sched: [1:1.00]
; ;
; ATOM-LABEL: test_psrlw: ; ATOM-LABEL: test_psrlw:
; ATOM: # BB#0: ; ATOM: # BB#0:
; ATOM-NEXT: psrlw %xmm1, %xmm0 # sched: [2:1.00] ; ATOM-NEXT: psrlw %xmm1, %xmm0 # sched: [2:1.00]
; ATOM-NEXT: psrlw (%rdi), %xmm0 # sched: [3:1.50] ; ATOM-NEXT: psrlw (%rdi), %xmm0 # sched: [3:1.50]
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psrlw: ; ZNVER1-LABEL: test_psrlw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; ZNVER1-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; ZNVER1-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %1, <8 x i16> %2)
%4 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %3, i32 2) %4 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %3, i32 2)
ret <8 x i16> %4 ret <8 x i16> %4
} }
declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone
define <16 x i8> @test_psubb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_psubb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
; GENERIC-LABEL: test_psubb: ; GENERIC-LABEL: test_psubb:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
; GENERIC-NEXT: psubb %xmm1, %xmm0 # sched: [1:0.50] ; GENERIC-NEXT: psubb %xmm1, %xmm0 # sched: [1:0.50]
; GENERIC-NEXT: psubb (%rdi), %xmm0 # sched: [7:0.50] ; GENERIC-NEXT: psubb (%rdi), %xmm0 # sched: [7:0.50]
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; BTVER2-LABEL: test_psubb: ; BTVER2-LABEL: test_psubb:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubb: ; ZNVER1-LABEL: test_psubb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = sub <16 x i8> %a0, %a1 %1 = sub <16 x i8> %a0, %a1
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = sub <16 x i8> %1, %2 %3 = sub <16 x i8> %1, %2
ret <16 x i8> %3 ret <16 x i8> %3
} }
define <4 x i32> @test_psubd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) { define <4 x i32> @test_psubd(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
; GENERIC-LABEL: test_psubd: ; GENERIC-LABEL: test_psubd:
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; ;
; BTVER2-LABEL: test_psubd: ; BTVER2-LABEL: test_psubd:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubd: ; ZNVER1-LABEL: test_psubd:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = sub <4 x i32> %a0, %a1 %1 = sub <4 x i32> %a0, %a1
%2 = load <4 x i32>, <4 x i32> *%a2, align 16 %2 = load <4 x i32>, <4 x i32> *%a2, align 16
%3 = sub <4 x i32> %1, %2 %3 = sub <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <2 x i64> @test_psubq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_psubq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_psubq: ; GENERIC-LABEL: test_psubq:
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; BTVER2-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubq: ; ZNVER1-LABEL: test_psubq:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = sub <2 x i64> %a0, %a1 %1 = sub <2 x i64> %a0, %a1
%2 = load <2 x i64>, <2 x i64> *%a2, align 16 %2 = load <2 x i64>, <2 x i64> *%a2, align 16
%3 = sub <2 x i64> %1, %2 %3 = sub <2 x i64> %1, %2
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <16 x i8> @test_psubsb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_psubsb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
; GENERIC-LABEL: test_psubsb: ; GENERIC-LABEL: test_psubsb:
; GENERIC: # BB#0: ; GENERIC: # BB#0:
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; BTVER2-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubsb: ; ZNVER1-LABEL: test_psubsb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %a0, <16 x i8> %a1) %1 = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %a0, <16 x i8> %a1)
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %1, <16 x i8> %2) %3 = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %1, <16 x i8> %2)
ret <16 x i8> %3 ret <16 x i8> %3
} }
declare <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8>, <16 x i8>) nounwind readnone
define <8 x i16> @test_psubsw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_psubsw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
; GENERIC-LABEL: test_psubsw: ; GENERIC-LABEL: test_psubsw:
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; BTVER2-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubsw: ; ZNVER1-LABEL: test_psubsw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone
define <16 x i8> @test_psubusb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_psubusb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubusb: ; ZNVER1-LABEL: test_psubusb:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %a0, <16 x i8> %a1) %1 = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %a0, <16 x i8> %a1)
%2 = load <16 x i8>, <16 x i8> *%a2, align 16 %2 = load <16 x i8>, <16 x i8> *%a2, align 16
%3 = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %1, <16 x i8> %2) %3 = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %1, <16 x i8> %2)
ret <16 x i8> %3 ret <16 x i8> %3
} }
declare <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8>, <16 x i8>) nounwind readnone
define <8 x i16> @test_psubusw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_psubusw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; ;
; BTVER2-LABEL: test_psubusw: ; BTVER2-LABEL: test_psubusw:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubusw: ; ZNVER1-LABEL: test_psubusw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %a0, <8 x i16> %a1) %1 = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %a0, <8 x i16> %a1)
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %1, <8 x i16> %2) %3 = call <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16> %1, <8 x i16> %2)
ret <8 x i16> %3 ret <8 x i16> %3
} }
declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnone
define <8 x i16> @test_psubw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) { define <8 x i16> @test_psubw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; BTVER2-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [6:1.00] ; BTVER2-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_psubw: ; ZNVER1-LABEL: test_psubw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [8:0.50] ; ZNVER1-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = sub <8 x i16> %a0, %a1 %1 = sub <8 x i16> %a0, %a1
%2 = load <8 x i16>, <8 x i16> *%a2, align 16 %2 = load <8 x i16>, <8 x i16> *%a2, align 16
%3 = sub <8 x i16> %1, %2 %3 = sub <8 x i16> %1, %2
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <16 x i8> @test_punpckhbw(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { define <16 x i8> @test_punpckhbw(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
; GENERIC-LABEL: test_punpckhbw: ; GENERIC-LABEL: test_punpckhbw:
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; BTVER2-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] sched: [1:0.50] ; BTVER2-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] sched: [1:0.50]
; BTVER2-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [6:1.00] ; BTVER2-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [6:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_punpckhbw: ; ZNVER1-LABEL: test_punpckhbw:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] sched: [1:0.25] ; ZNVER1-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] sched: [1:0.25]
; ZNVER1-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [8:0.50] ; ZNVER1-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [8:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i3