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Differential D36617 Diff 111898 test/CodeGen/X86/aes-schedule.ll

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test/CodeGen/X86/aes-schedule.ll

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; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_aesdec: ; ZNVER1-LABEL: test_aesdec:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:0.50] ; ZNVER1-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [11:0.50] ; ZNVER1-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a2, align 16 %1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1) %2 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %2, <2 x i64> %1) %3 = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3 ret <2 x i64> %3
} }
declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesdeclast(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_aesdeclast(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
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; BTVER2-LABEL: test_aesdeclast: ; BTVER2-LABEL: test_aesdeclast:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_aesdeclast: ; ZNVER1-LABEL: test_aesdeclast:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:0.50] ; ZNVER1-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [11:0.50] ; ZNVER1-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a2, align 16 %1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1) %2 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %2, <2 x i64> %1) %3 = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3 ret <2 x i64> %3
} }
declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesenc(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_aesenc(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
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; ;
; BTVER2-LABEL: test_aesenc: ; BTVER2-LABEL: test_aesenc:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_aesenc: ; ZNVER1-LABEL: test_aesenc:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:0.50] ; ZNVER1-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [11:0.50] ; ZNVER1-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a2, align 16 %1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1) %2 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %2, <2 x i64> %1) %3 = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3 ret <2 x i64> %3
} }
declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesenclast(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) { define <2 x i64> @test_aesenclast(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
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; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_aesenclast: ; BTVER2-LABEL: test_aesenclast:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [8:1.00] ; BTVER2-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_aesenclast: ; ZNVER1-LABEL: test_aesenclast:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:0.50] ; ZNVER1-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [11:0.50] ; ZNVER1-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [11:0.50]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a2, align 16 %1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1) %2 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1)
%3 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %2, <2 x i64> %1) %3 = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %2, <2 x i64> %1)
ret <2 x i64> %3 ret <2 x i64> %3
} }
declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>)
define <2 x i64> @test_aesimc(<2 x i64> %a0, <2 x i64> *%a1) { define <2 x i64> @test_aesimc(<2 x i64> %a0, <2 x i64> *%a1) {
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; ;
; BTVER2-LABEL: test_aesimc: ; BTVER2-LABEL: test_aesimc:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaesimc (%rdi), %xmm1 # sched: [7:1.00] ; BTVER2-NEXT: vaesimc (%rdi), %xmm1 # sched: [7:1.00]
; BTVER2-NEXT: vaesimc %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vaesimc %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_aesimc: ; ZNVER1-LABEL: test_aesimc:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaesimc (%rdi), %xmm1 # sched: [11:0.50] ; ZNVER1-NEXT: vaesimc (%rdi), %xmm1 # sched: [11:0.50]
; ZNVER1-NEXT: vaesimc %xmm0, %xmm0 # sched: [4:0.50] ; ZNVER1-NEXT: vaesimc %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a1, align 16 %1 = load <2 x i64>, <2 x i64> *%a1, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0) %2 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0)
%3 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %1) %3 = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %1)
%4 = or <2 x i64> %2, %3 %4 = or <2 x i64> %2, %3
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>) declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>)
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; HASWELL-NEXT: retq # sched: [1:1.00] ; HASWELL-NEXT: retq # sched: [1:1.00]
; ;
; BTVER2-LABEL: test_aeskeygenassist: ; BTVER2-LABEL: test_aeskeygenassist:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [7:1.00] ; BTVER2-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [7:1.00]
; BTVER2-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [2:1.00] ; BTVER2-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_aeskeygenassist: ; ZNVER1-LABEL: test_aeskeygenassist:
; ZNVER1: # BB#0: ; ZNVER1: # BB#0:
; ZNVER1-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [11:0.50] ; ZNVER1-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [11:0.50]
; ZNVER1-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [4:0.50] ; ZNVER1-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [4:0.50]
; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25] ; ZNVER1-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
; ZNVER1-NEXT: retq # sched: [5:0.50] ; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = load <2 x i64>, <2 x i64> *%a1, align 16 %1 = load <2 x i64>, <2 x i64> *%a1, align 16
%2 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7) %2 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %a0, i8 7)
%3 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %1, i8 7) %3 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %1, i8 7)
%4 = or <2 x i64> %2, %3 %4 = or <2 x i64> %2, %3
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8)