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lib/Target/RISCV/RISCVInstrInfo.td
| //===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===// | //===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===// | ||||
| // | // | ||||
| // The LLVM Compiler Infrastructure | // The LLVM Compiler Infrastructure | ||||
| // | // | ||||
| // This file is distributed under the University of Illinois Open Source | // This file is distributed under the University of Illinois Open Source | ||||
| // License. See LICENSE.TXT for details. | // License. See LICENSE.TXT for details. | ||||
| // | // | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // | // | ||||
| // This file describes the RISC-V instructions in TableGen format. | // This file describes the RISC-V instructions in TableGen format. | ||||
| // | // | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| include "RISCVInstrFormats.td" | include "RISCVInstrFormats.td" | ||||
| def SDT_RISCVCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, | |||||
| SDTCisVT<1, i32>]>; | |||||
| def SDT_RISCVCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, | |||||
| SDTCisVT<1, i32>]>; | |||||
| def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; | |||||
| def Call : SDNode<"RISCVISD::CALL", SDT_RISCVCall, | |||||
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, | |||||
| SDNPVariadic]>; | |||||
| def RetFlag : SDNode<"RISCVISD::RET_FLAG", SDTNone, | def RetFlag : SDNode<"RISCVISD::RET_FLAG", SDTNone, | ||||
| [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; | [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; | ||||
| def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_RISCVCallSeqStart, | |||||
| [SDNPHasChain, SDNPOutGlue]>; | |||||
| def CallSeqEnd : SDNode<"ISD::CALLSEQ_END", SDT_RISCVCallSeqEnd, | |||||
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; | |||||
| // Operands | // Operands | ||||
| class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass { | class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass { | ||||
| let Name = prefix # "Imm" # width # suffix; | let Name = prefix # "Imm" # width # suffix; | ||||
| let RenderMethod = "addImmOperands"; | let RenderMethod = "addImmOperands"; | ||||
| let DiagnosticType = !strconcat("Invalid", Name); | let DiagnosticType = !strconcat("Invalid", Name); | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | |||||
| // is adopted. | // is adopted. | ||||
| def LUI : FU<0b0110111, (outs GPR:$rd), (ins uimm20:$imm20), | def LUI : FU<0b0110111, (outs GPR:$rd), (ins uimm20:$imm20), | ||||
| "lui\t$rd, $imm20", []>; | "lui\t$rd, $imm20", []>; | ||||
| def AUIPC : FU<0b0010111, (outs GPR:$rd), (ins uimm20:$imm20), | def AUIPC : FU<0b0010111, (outs GPR:$rd), (ins uimm20:$imm20), | ||||
| "auipc\t$rd, $imm20", []>; | "auipc\t$rd, $imm20", []>; | ||||
| let isCall=1 in { | |||||
| def JAL : FUJ<0b1101111, (outs GPR:$rd), (ins simm21_lsb0:$imm20), | def JAL : FUJ<0b1101111, (outs GPR:$rd), (ins simm21_lsb0:$imm20), | ||||
| "jal\t$rd, $imm20", []>; | "jal\t$rd, $imm20", []>; | ||||
| } | |||||
| let isTerminator=1, isBarrier=1 in { | let isTerminator=1, isBarrier=1 in { | ||||
| def PseudoBR : Pseudo<(outs), (ins simm21_lsb0:$imm20), [(br bb:$imm20)]>, | def PseudoBR : Pseudo<(outs), (ins simm21_lsb0:$imm20), [(br bb:$imm20)]>, | ||||
| PseudoInstExpansion<(JAL X0_32, simm21_lsb0:$imm20)>; | PseudoInstExpansion<(JAL X0_32, simm21_lsb0:$imm20)>; | ||||
| } | } | ||||
| let isCall=1 in { | |||||
| def JALR : FI<0b000, 0b1100111, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), | def JALR : FI<0b000, 0b1100111, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), | ||||
| "jalr\t$rd, $rs1, $imm12", []>; | "jalr\t$rd, $rs1, $imm12", []>; | ||||
| } | |||||
| let isCall=1, Defs=[X1_32] in { | |||||
| def PseudoCALL : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>, | |||||
| PseudoInstExpansion<(JALR X1_32, GPR:$rs1, 0)>; | |||||
| } | |||||
| let isReturn=1, isTerminator=1, isBarrier=1 in { | let isReturn=1, isTerminator=1, isBarrier=1 in { | ||||
| def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>, | def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>, | ||||
| PseudoInstExpansion<(JALR X0_32, X1_32, 0)>; | PseudoInstExpansion<(JALR X0_32, X1_32, 0)>; | ||||
| } | } | ||||
| // Pessimistically assume the stack pointer will be clobbered | |||||
| let Defs = [X2_32], Uses = [X2_32] in { | |||||
| def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), | |||||
| [(CallSeqStart timm:$amt1, timm:$amt2)]>; | |||||
| def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), | |||||
| [(CallSeqEnd timm:$amt1, timm:$amt2)]>; | |||||
| } | |||||
| class Bcc<bits<3> funct3, string OpcodeStr, PatFrag CondOp> : | class Bcc<bits<3> funct3, string OpcodeStr, PatFrag CondOp> : | ||||
| FSB<funct3, 0b1100011, (outs), (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), | FSB<funct3, 0b1100011, (outs), (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12), | ||||
| OpcodeStr#"\t$rs1, $rs2, $imm12", [(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12)]> { | OpcodeStr#"\t$rs1, $rs2, $imm12", [(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12)]> { | ||||
| let isBranch = 1; | let isBranch = 1; | ||||
| let isTerminator = 1; | let isTerminator = 1; | ||||
| } | } | ||||
| def BEQ : Bcc<0b000, "beq", seteq>; | def BEQ : Bcc<0b000, "beq", seteq>; | ||||
| ▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines | |||||
| def CSRRWI : CSR_ri<0b101, "csrrwi">; | def CSRRWI : CSR_ri<0b101, "csrrwi">; | ||||
| def CSRRSI : CSR_ri<0b110, "csrrsi">; | def CSRRSI : CSR_ri<0b110, "csrrsi">; | ||||
| def CSRRCI : CSR_ri<0b111, "csrrci">; | def CSRRCI : CSR_ri<0b111, "csrrci">; | ||||
| // signed 12-bit immediate | // signed 12-bit immediate | ||||
| def : Pat<(simm12:$imm), (ADDI X0_32, simm12:$imm)>; | def : Pat<(simm12:$imm), (ADDI X0_32, simm12:$imm)>; | ||||
kparzysz: Please add spaces between Defs and []. | |||||
| // 32-bit immediate | // 32-bit immediate | ||||
| def : Pat<(i32 imm:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>; | def : Pat<(i32 imm:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>; | ||||
Please add spaces between Defs and [].