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lib/Target/PowerPC/PPCTargetMachine.cpp
| Show All 34 Lines | |||||
| #include "llvm/Target/TargetOptions.h" | #include "llvm/Target/TargetOptions.h" | ||||
| #include "llvm/Transforms/Scalar.h" | #include "llvm/Transforms/Scalar.h" | ||||
| #include <cassert> | #include <cassert> | ||||
| #include <memory> | #include <memory> | ||||
| #include <string> | #include <string> | ||||
| using namespace llvm; | using namespace llvm; | ||||
| static cl::opt<bool> | |||||
| DisableBranchCoalescing("disable-ppc-branch-coalesce", cl::Hidden, | |||||
| cl::desc("disable coalescing of duplicate branches for PPC")); | |||||
| static cl:: | static cl:: | ||||
| opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, | opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, | ||||
| cl::desc("Disable CTR loops for PPC")); | cl::desc("Disable CTR loops for PPC")); | ||||
| static cl:: | static cl:: | ||||
| opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, | opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, | ||||
| cl::desc("Disable PPC loop preinc prep")); | cl::desc("Disable PPC loop preinc prep")); | ||||
| ▲ Show 20 Lines • Show All 322 Lines • ▼ Show 20 Lines | if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) | ||||
| addPass(createPPCCTRLoopsVerify()); | addPass(createPPCCTRLoopsVerify()); | ||||
| #endif | #endif | ||||
| addPass(createPPCVSXCopyPass()); | addPass(createPPCVSXCopyPass()); | ||||
| return false; | return false; | ||||
| } | } | ||||
| void PPCPassConfig::addMachineSSAOptimization() { | void PPCPassConfig::addMachineSSAOptimization() { | ||||
| // PPCBranchCoalescingPass need to be done before machine sinking | |||||
| // since it merges empty blocks. | |||||
| if (!DisableBranchCoalescing && getOptLevel() != CodeGenOpt::None) | |||||
| addPass(createPPCBranchCoalescingPass()); | |||||
| TargetPassConfig::addMachineSSAOptimization(); | TargetPassConfig::addMachineSSAOptimization(); | ||||
| // For little endian, remove where possible the vector swap instructions | // For little endian, remove where possible the vector swap instructions | ||||
| // introduced at code generation to normalize vector element order. | // introduced at code generation to normalize vector element order. | ||||
| if (TM->getTargetTriple().getArch() == Triple::ppc64le && | if (TM->getTargetTriple().getArch() == Triple::ppc64le && | ||||
| !DisableVSXSwapRemoval) | !DisableVSXSwapRemoval) | ||||
| addPass(createPPCVSXSwapRemovalPass()); | addPass(createPPCVSXSwapRemovalPass()); | ||||
| // Target-specific peephole cleanups performed after instruction | // Target-specific peephole cleanups performed after instruction | ||||
| // selection. | // selection. | ||||
| ▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines | |||||