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lib/Target/RISCV/RISCVMCInstLower.cpp
| Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines | bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, | ||||
| default: | default: | ||||
| llvm_unreachable("unknown operand type"); | llvm_unreachable("unknown operand type"); | ||||
| case MachineOperand::MO_Register: | case MachineOperand::MO_Register: | ||||
| // Ignore all implicit register operands. | // Ignore all implicit register operands. | ||||
| if (MO.isImplicit()) | if (MO.isImplicit()) | ||||
| return false; | return false; | ||||
| MCOp = MCOperand::createReg(MO.getReg()); | MCOp = MCOperand::createReg(MO.getReg()); | ||||
| break; | break; | ||||
| case MachineOperand::MO_RegisterMask: | |||||
| // Regmasks are like implicit defs. | |||||
| return false; | |||||
| case MachineOperand::MO_Immediate: | case MachineOperand::MO_Immediate: | ||||
| MCOp = MCOperand::createImm(MO.getImm()); | MCOp = MCOperand::createImm(MO.getImm()); | ||||
| break; | break; | ||||
| case MachineOperand::MO_MachineBasicBlock: | case MachineOperand::MO_MachineBasicBlock: | ||||
| MCOp = MCOperand::createExpr( | MCOp = MCOperand::createExpr( | ||||
| MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), AP.OutContext)); | MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), AP.OutContext)); | ||||
| break; | break; | ||||
| case MachineOperand::MO_GlobalAddress: | case MachineOperand::MO_GlobalAddress: | ||||
| Show All 16 Lines | |||||