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	; RUN: llc -O3 < %s -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-gep-opt=false -verify-machineinstrs \| FileCheck %s			; RUN: llc -O3 < %s -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-gep-opt=false -verify-machineinstrs \| FileCheck %s
	target triple = "arm64-apple-ios"			target triple = "arm64-apple-ios"

	; rdar://12462006			; rdar://12462006
	; CSE between "icmp reg reg" and "sub reg reg".			; CSE between "icmp reg reg" and "sub reg reg".
	; Both can be in the same basic block or in different basic blocks.			; Both can be in the same basic block or in different basic blocks.
	define i8* @t1(i8* %base, i32* nocapture %offset, i32 %size) nounwind {			define i8* @t1(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
	entry:			entry:
	; CHECK-LABEL: t1:			; CHECK-LABEL: t1:
	; CHECK: subs			; CHECK: subs
	; CHECK-NOT: cmp			; CHECK-NOT: cmp
	; CHECK-NOT: sub			; CHECK-NOT: sub
	; CHECK: b.ge			; CHECK: b.lt
	; CHECK: sub			; CHECK: sub
	; CHECK: sub			; CHECK: sub
	; CHECK-NOT: sub			; CHECK-NOT: sub
	; CHECK: ret			; CHECK: ret
	%0 = load i32, i32* %offset, align 4			%0 = load i32, i32* %offset, align 4
	%cmp = icmp slt i32 %0, %size			%cmp = icmp slt i32 %0, %size
	%s = sub nsw i32 %0, %size			%s = sub nsw i32 %0, %size
	br i1 %cmp, label %return, label %if.end			br i1 %cmp, label %return, label %if.end
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