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Differential D35844 Diff 109065 test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll

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test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll

Show First 20 Lines • Show All 316 Lines • ▼ Show 20 Lines
; SSE2-SSSE3-NEXT: movd %ebp, %xmm2 ; SSE2-SSSE3-NEXT: movd %ebp, %xmm2
; SSE2-SSSE3-NEXT: shrq $7, %rax ; SSE2-SSSE3-NEXT: shrq $7, %rax
; SSE2-SSSE3-NEXT: movd %eax, %xmm3 ; SSE2-SSSE3-NEXT: movd %eax, %xmm3
; SSE2-SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3],xmm2[4],xmm3[4],xmm2[5],xmm3[5],xmm2[6],xmm3[6],xmm2[7],xmm3[7] ; SSE2-SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3],xmm2[4],xmm3[4],xmm2[5],xmm3[5],xmm2[6],xmm3[6],xmm2[7],xmm3[7]
; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] ; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3]
; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1] ; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-SSSE3-NEXT: popq %rbx ; SSE2-SSSE3-NEXT: popq %rbx
; SSE2-SSSE3-NEXT: .Lcfi12:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 48
; SSE2-SSSE3-NEXT: popq %r12 ; SSE2-SSSE3-NEXT: popq %r12
; SSE2-SSSE3-NEXT: .Lcfi13:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 40
; SSE2-SSSE3-NEXT: popq %r13 ; SSE2-SSSE3-NEXT: popq %r13
; SSE2-SSSE3-NEXT: .Lcfi14:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 32
; SSE2-SSSE3-NEXT: popq %r14 ; SSE2-SSSE3-NEXT: popq %r14
; SSE2-SSSE3-NEXT: .Lcfi15:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 24
; SSE2-SSSE3-NEXT: popq %r15 ; SSE2-SSSE3-NEXT: popq %r15
; SSE2-SSSE3-NEXT: .Lcfi16:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 16
; SSE2-SSSE3-NEXT: popq %rbp ; SSE2-SSSE3-NEXT: popq %rbp
; SSE2-SSSE3-NEXT: .Lcfi17:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 8
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX12-LABEL: ext_i16_16i8: ; AVX12-LABEL: ext_i16_16i8:
; AVX12: # BB#0: ; AVX12: # BB#0:
; AVX12-NEXT: movw %di, -{{[0-9]+}}(%rsp) ; AVX12-NEXT: movw %di, -{{[0-9]+}}(%rsp)
; AVX12-NEXT: movswq -{{[0-9]+}}(%rsp), %rax ; AVX12-NEXT: movswq -{{[0-9]+}}(%rsp), %rax
; AVX12-NEXT: movq %rax, %rcx ; AVX12-NEXT: movq %rax, %rcx
; AVX12-NEXT: shlq $62, %rcx ; AVX12-NEXT: shlq $62, %rcx
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; AVX1-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1
; AVX1-NEXT: shlq $57, %rsi ; AVX1-NEXT: shlq $57, %rsi
; AVX1-NEXT: sarq $63, %rsi ; AVX1-NEXT: sarq $63, %rsi
; AVX1-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1
; AVX1-NEXT: shrq $7, %rbp ; AVX1-NEXT: shrq $7, %rbp
; AVX1-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: .Lcfi12:
; AVX1-NEXT: .cfi_def_cfa_offset 48
; AVX1-NEXT: popq %r12 ; AVX1-NEXT: popq %r12
; AVX1-NEXT: .Lcfi13:
; AVX1-NEXT: .cfi_def_cfa_offset 40
; AVX1-NEXT: popq %r13 ; AVX1-NEXT: popq %r13
; AVX1-NEXT: .Lcfi14:
; AVX1-NEXT: .cfi_def_cfa_offset 32
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: .Lcfi15:
; AVX1-NEXT: .cfi_def_cfa_offset 24
; AVX1-NEXT: popq %r15 ; AVX1-NEXT: popq %r15
; AVX1-NEXT: .Lcfi16:
; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi17:
; AVX1-NEXT: .cfi_def_cfa_offset 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: ext_i16_16i16: ; AVX2-LABEL: ext_i16_16i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi0: ; AVX2-NEXT: .Lcfi0:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: pushq %r15 ; AVX2-NEXT: pushq %r15
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; AVX2-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrw $5, %edx, %xmm1, %xmm1
; AVX2-NEXT: shlq $57, %rsi ; AVX2-NEXT: shlq $57, %rsi
; AVX2-NEXT: sarq $63, %rsi ; AVX2-NEXT: sarq $63, %rsi
; AVX2-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrw $6, %esi, %xmm1, %xmm1
; AVX2-NEXT: shrq $7, %rbp ; AVX2-NEXT: shrq $7, %rbp
; AVX2-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrw $7, %ebp, %xmm1, %xmm1
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: .Lcfi12:
; AVX2-NEXT: .cfi_def_cfa_offset 48
; AVX2-NEXT: popq %r12 ; AVX2-NEXT: popq %r12
; AVX2-NEXT: .Lcfi13:
; AVX2-NEXT: .cfi_def_cfa_offset 40
; AVX2-NEXT: popq %r13 ; AVX2-NEXT: popq %r13
; AVX2-NEXT: .Lcfi14:
; AVX2-NEXT: .cfi_def_cfa_offset 32
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: .Lcfi15:
; AVX2-NEXT: .cfi_def_cfa_offset 24
; AVX2-NEXT: popq %r15 ; AVX2-NEXT: popq %r15
; AVX2-NEXT: .Lcfi16:
; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi17:
; AVX2-NEXT: .cfi_def_cfa_offset 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i16_16i16: ; AVX512-LABEL: ext_i16_16i16:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: kmovd %edi, %k0 ; AVX512-NEXT: kmovd %edi, %k0
; AVX512-NEXT: vpmovm2w %k0, %ymm0 ; AVX512-NEXT: vpmovm2w %k0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i16 %a0 to <16 x i1> %1 = bitcast i16 %a0 to <16 x i1>
%2 = sext <16 x i1> %1 to <16 x i16> %2 = sext <16 x i1> %1 to <16 x i16>
ret <16 x i16> %2 ret <16 x i16> %2
} }
define <32 x i8> @ext_i32_32i8(i32 %a0) { define <32 x i8> @ext_i32_32i8(i32 %a0) {
; SSE2-SSSE3-LABEL: ext_i32_32i8: ; SSE2-SSSE3-LABEL: ext_i32_32i8:
; SSE2-SSSE3: # BB#0: ; SSE2-SSSE3: # BB#0:
; SSE2-SSSE3-NEXT: pushq %rbp ; SSE2-SSSE3-NEXT: pushq %rbp
; SSE2-SSSE3-NEXT: .Lcfi12: ; SSE2-SSSE3-NEXT: .Lcfi18:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 16 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 16
; SSE2-SSSE3-NEXT: pushq %r15 ; SSE2-SSSE3-NEXT: pushq %r15
; SSE2-SSSE3-NEXT: .Lcfi13: ; SSE2-SSSE3-NEXT: .Lcfi19:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 24 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 24
; SSE2-SSSE3-NEXT: pushq %r14 ; SSE2-SSSE3-NEXT: pushq %r14
; SSE2-SSSE3-NEXT: .Lcfi14: ; SSE2-SSSE3-NEXT: .Lcfi20:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 32 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 32
; SSE2-SSSE3-NEXT: pushq %r13 ; SSE2-SSSE3-NEXT: pushq %r13
; SSE2-SSSE3-NEXT: .Lcfi15: ; SSE2-SSSE3-NEXT: .Lcfi21:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 40 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 40
; SSE2-SSSE3-NEXT: pushq %r12 ; SSE2-SSSE3-NEXT: pushq %r12
; SSE2-SSSE3-NEXT: .Lcfi16: ; SSE2-SSSE3-NEXT: .Lcfi22:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 48 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 48
; SSE2-SSSE3-NEXT: pushq %rbx ; SSE2-SSSE3-NEXT: pushq %rbx
; SSE2-SSSE3-NEXT: .Lcfi17: ; SSE2-SSSE3-NEXT: .Lcfi23:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 56 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 56
; SSE2-SSSE3-NEXT: .Lcfi18: ; SSE2-SSSE3-NEXT: .Lcfi24:
; SSE2-SSSE3-NEXT: .cfi_offset %rbx, -56 ; SSE2-SSSE3-NEXT: .cfi_offset %rbx, -56
; SSE2-SSSE3-NEXT: .Lcfi19: ; SSE2-SSSE3-NEXT: .Lcfi25:
; SSE2-SSSE3-NEXT: .cfi_offset %r12, -48 ; SSE2-SSSE3-NEXT: .cfi_offset %r12, -48
; SSE2-SSSE3-NEXT: .Lcfi20: ; SSE2-SSSE3-NEXT: .Lcfi26:
; SSE2-SSSE3-NEXT: .cfi_offset %r13, -40 ; SSE2-SSSE3-NEXT: .cfi_offset %r13, -40
; SSE2-SSSE3-NEXT: .Lcfi21: ; SSE2-SSSE3-NEXT: .Lcfi27:
; SSE2-SSSE3-NEXT: .cfi_offset %r14, -32 ; SSE2-SSSE3-NEXT: .cfi_offset %r14, -32
; SSE2-SSSE3-NEXT: .Lcfi22: ; SSE2-SSSE3-NEXT: .Lcfi28:
; SSE2-SSSE3-NEXT: .cfi_offset %r15, -24 ; SSE2-SSSE3-NEXT: .cfi_offset %r15, -24
; SSE2-SSSE3-NEXT: .Lcfi23: ; SSE2-SSSE3-NEXT: .Lcfi29:
; SSE2-SSSE3-NEXT: .cfi_offset %rbp, -16 ; SSE2-SSSE3-NEXT: .cfi_offset %rbp, -16
; SSE2-SSSE3-NEXT: movw %di, -{{[0-9]+}}(%rsp) ; SSE2-SSSE3-NEXT: movw %di, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: shrl $16, %edi ; SSE2-SSSE3-NEXT: shrl $16, %edi
; SSE2-SSSE3-NEXT: movw %di, -{{[0-9]+}}(%rsp) ; SSE2-SSSE3-NEXT: movw %di, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movswq -{{[0-9]+}}(%rsp), %rbx ; SSE2-SSSE3-NEXT: movswq -{{[0-9]+}}(%rsp), %rbx
; SSE2-SSSE3-NEXT: movq %rbx, %r8 ; SSE2-SSSE3-NEXT: movq %rbx, %r8
; SSE2-SSSE3-NEXT: movq %rbx, %r9 ; SSE2-SSSE3-NEXT: movq %rbx, %r9
; SSE2-SSSE3-NEXT: movq %rbx, %r10 ; SSE2-SSSE3-NEXT: movq %rbx, %r10
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; SSE2-SSSE3-NEXT: movd %ebp, %xmm4 ; SSE2-SSSE3-NEXT: movd %ebp, %xmm4
; SSE2-SSSE3-NEXT: shrq $7, %rsi ; SSE2-SSSE3-NEXT: shrq $7, %rsi
; SSE2-SSSE3-NEXT: movd %esi, %xmm5 ; SSE2-SSSE3-NEXT: movd %esi, %xmm5
; SSE2-SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3],xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7] ; SSE2-SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1],xmm4[2],xmm5[2],xmm4[3],xmm5[3],xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7]
; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] ; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; SSE2-SSSE3-NEXT: popq %rbx ; SSE2-SSSE3-NEXT: popq %rbx
; SSE2-SSSE3-NEXT: .Lcfi30:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 48
; SSE2-SSSE3-NEXT: popq %r12 ; SSE2-SSSE3-NEXT: popq %r12
; SSE2-SSSE3-NEXT: .Lcfi31:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 40
; SSE2-SSSE3-NEXT: popq %r13 ; SSE2-SSSE3-NEXT: popq %r13
; SSE2-SSSE3-NEXT: .Lcfi32:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 32
; SSE2-SSSE3-NEXT: popq %r14 ; SSE2-SSSE3-NEXT: popq %r14
; SSE2-SSSE3-NEXT: .Lcfi33:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 24
; SSE2-SSSE3-NEXT: popq %r15 ; SSE2-SSSE3-NEXT: popq %r15
; SSE2-SSSE3-NEXT: .Lcfi34:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 16
; SSE2-SSSE3-NEXT: popq %rbp ; SSE2-SSSE3-NEXT: popq %rbp
; SSE2-SSSE3-NEXT: .Lcfi35:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 8
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX1-LABEL: ext_i32_32i8: ; AVX1-LABEL: ext_i32_32i8:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi12: ; AVX1-NEXT: .Lcfi18:
; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi13: ; AVX1-NEXT: .Lcfi19:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: .Lcfi14: ; AVX1-NEXT: .Lcfi20:
; AVX1-NEXT: .cfi_def_cfa_register %rbp ; AVX1-NEXT: .cfi_def_cfa_register %rbp
; AVX1-NEXT: pushq %r15 ; AVX1-NEXT: pushq %r15
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %r13 ; AVX1-NEXT: pushq %r13
; AVX1-NEXT: pushq %r12 ; AVX1-NEXT: pushq %r12
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $64, %rsp ; AVX1-NEXT: subq $64, %rsp
; AVX1-NEXT: .Lcfi15: ; AVX1-NEXT: .Lcfi21:
; AVX1-NEXT: .cfi_offset %rbx, -56 ; AVX1-NEXT: .cfi_offset %rbx, -56
; AVX1-NEXT: .Lcfi16: ; AVX1-NEXT: .Lcfi22:
; AVX1-NEXT: .cfi_offset %r12, -48 ; AVX1-NEXT: .cfi_offset %r12, -48
; AVX1-NEXT: .Lcfi17: ; AVX1-NEXT: .Lcfi23:
; AVX1-NEXT: .cfi_offset %r13, -40 ; AVX1-NEXT: .cfi_offset %r13, -40
; AVX1-NEXT: .Lcfi18: ; AVX1-NEXT: .Lcfi24:
; AVX1-NEXT: .cfi_offset %r14, -32 ; AVX1-NEXT: .cfi_offset %r14, -32
; AVX1-NEXT: .Lcfi19: ; AVX1-NEXT: .Lcfi25:
; AVX1-NEXT: .cfi_offset %r15, -24 ; AVX1-NEXT: .cfi_offset %r15, -24
; AVX1-NEXT: movl %edi, (%rsp) ; AVX1-NEXT: movl %edi, (%rsp)
; AVX1-NEXT: movslq (%rsp), %rdx ; AVX1-NEXT: movslq (%rsp), %rdx
; AVX1-NEXT: movq %rdx, %rcx ; AVX1-NEXT: movq %rdx, %rcx
; AVX1-NEXT: shlq $47, %rcx ; AVX1-NEXT: shlq $47, %rcx
; AVX1-NEXT: sarq $63, %rcx ; AVX1-NEXT: sarq $63, %rcx
; AVX1-NEXT: vmovd %ecx, %xmm0 ; AVX1-NEXT: vmovd %ecx, %xmm0
; AVX1-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill ; AVX1-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: leaq -40(%rbp), %rsp ; AVX1-NEXT: leaq -40(%rbp), %rsp
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r12 ; AVX1-NEXT: popq %r12
; AVX1-NEXT: popq %r13 ; AVX1-NEXT: popq %r13
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: popq %r15 ; AVX1-NEXT: popq %r15
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi26:
; AVX1-NEXT: .cfi_def_cfa %rsp, 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: ext_i32_32i8: ; AVX2-LABEL: ext_i32_32i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi12: ; AVX2-NEXT: .Lcfi18:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi13: ; AVX2-NEXT: .Lcfi19:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: movq %rsp, %rbp
; AVX2-NEXT: .Lcfi14: ; AVX2-NEXT: .Lcfi20:
; AVX2-NEXT: .cfi_def_cfa_register %rbp ; AVX2-NEXT: .cfi_def_cfa_register %rbp
; AVX2-NEXT: pushq %r15 ; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %r13 ; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12 ; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: andq $-32, %rsp
; AVX2-NEXT: subq $64, %rsp ; AVX2-NEXT: subq $64, %rsp
; AVX2-NEXT: .Lcfi15: ; AVX2-NEXT: .Lcfi21:
; AVX2-NEXT: .cfi_offset %rbx, -56 ; AVX2-NEXT: .cfi_offset %rbx, -56
; AVX2-NEXT: .Lcfi16: ; AVX2-NEXT: .Lcfi22:
; AVX2-NEXT: .cfi_offset %r12, -48 ; AVX2-NEXT: .cfi_offset %r12, -48
; AVX2-NEXT: .Lcfi17: ; AVX2-NEXT: .Lcfi23:
; AVX2-NEXT: .cfi_offset %r13, -40 ; AVX2-NEXT: .cfi_offset %r13, -40
; AVX2-NEXT: .Lcfi18: ; AVX2-NEXT: .Lcfi24:
; AVX2-NEXT: .cfi_offset %r14, -32 ; AVX2-NEXT: .cfi_offset %r14, -32
; AVX2-NEXT: .Lcfi19: ; AVX2-NEXT: .Lcfi25:
; AVX2-NEXT: .cfi_offset %r15, -24 ; AVX2-NEXT: .cfi_offset %r15, -24
; AVX2-NEXT: movl %edi, (%rsp) ; AVX2-NEXT: movl %edi, (%rsp)
; AVX2-NEXT: movslq (%rsp), %rdx ; AVX2-NEXT: movslq (%rsp), %rdx
; AVX2-NEXT: movq %rdx, %rcx ; AVX2-NEXT: movq %rdx, %rcx
; AVX2-NEXT: shlq $47, %rcx ; AVX2-NEXT: shlq $47, %rcx
; AVX2-NEXT: sarq $63, %rcx ; AVX2-NEXT: sarq $63, %rcx
; AVX2-NEXT: vmovd %ecx, %xmm0 ; AVX2-NEXT: vmovd %ecx, %xmm0
; AVX2-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill ; AVX2-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill
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; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: leaq -40(%rbp), %rsp ; AVX2-NEXT: leaq -40(%rbp), %rsp
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12 ; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13 ; AVX2-NEXT: popq %r13
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15 ; AVX2-NEXT: popq %r15
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi26:
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i32_32i8: ; AVX512-LABEL: ext_i32_32i8:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: kmovd %edi, %k0 ; AVX512-NEXT: kmovd %edi, %k0
; AVX512-NEXT: vpmovm2b %k0, %ymm0 ; AVX512-NEXT: vpmovm2b %k0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i32 %a0 to <32 x i1> %1 = bitcast i32 %a0 to <32 x i1>
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; SSE2-SSSE3-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15] ; SSE2-SSSE3-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15]
; SSE2-SSSE3-NEXT: psllw $15, %xmm3 ; SSE2-SSSE3-NEXT: psllw $15, %xmm3
; SSE2-SSSE3-NEXT: psraw $15, %xmm3 ; SSE2-SSSE3-NEXT: psraw $15, %xmm3
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX1-LABEL: ext_i32_32i16: ; AVX1-LABEL: ext_i32_32i16:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi20: ; AVX1-NEXT: .Lcfi27:
; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi21: ; AVX1-NEXT: .Lcfi28:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: .Lcfi22: ; AVX1-NEXT: .Lcfi29:
; AVX1-NEXT: .cfi_def_cfa_register %rbp ; AVX1-NEXT: .cfi_def_cfa_register %rbp
; AVX1-NEXT: pushq %r15 ; AVX1-NEXT: pushq %r15
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %r13 ; AVX1-NEXT: pushq %r13
; AVX1-NEXT: pushq %r12 ; AVX1-NEXT: pushq %r12
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $128, %rsp ; AVX1-NEXT: subq $128, %rsp
; AVX1-NEXT: .Lcfi23: ; AVX1-NEXT: .Lcfi30:
; AVX1-NEXT: .cfi_offset %rbx, -56 ; AVX1-NEXT: .cfi_offset %rbx, -56
; AVX1-NEXT: .Lcfi24: ; AVX1-NEXT: .Lcfi31:
; AVX1-NEXT: .cfi_offset %r12, -48 ; AVX1-NEXT: .cfi_offset %r12, -48
; AVX1-NEXT: .Lcfi25: ; AVX1-NEXT: .Lcfi32:
; AVX1-NEXT: .cfi_offset %r13, -40 ; AVX1-NEXT: .cfi_offset %r13, -40
; AVX1-NEXT: .Lcfi26: ; AVX1-NEXT: .Lcfi33:
; AVX1-NEXT: .cfi_offset %r14, -32 ; AVX1-NEXT: .cfi_offset %r14, -32
; AVX1-NEXT: .Lcfi27: ; AVX1-NEXT: .Lcfi34:
; AVX1-NEXT: .cfi_offset %r15, -24 ; AVX1-NEXT: .cfi_offset %r15, -24
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: leaq -40(%rbp), %rsp ; AVX1-NEXT: leaq -40(%rbp), %rsp
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r12 ; AVX1-NEXT: popq %r12
; AVX1-NEXT: popq %r13 ; AVX1-NEXT: popq %r13
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: popq %r15 ; AVX1-NEXT: popq %r15
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi35:
; AVX1-NEXT: .cfi_def_cfa %rsp, 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: ext_i32_32i16: ; AVX2-LABEL: ext_i32_32i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi20: ; AVX2-NEXT: .Lcfi27:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi21: ; AVX2-NEXT: .Lcfi28:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: movq %rsp, %rbp
; AVX2-NEXT: .Lcfi22: ; AVX2-NEXT: .Lcfi29:
; AVX2-NEXT: .cfi_def_cfa_register %rbp ; AVX2-NEXT: .cfi_def_cfa_register %rbp
; AVX2-NEXT: pushq %r15 ; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %r13 ; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12 ; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: andq $-32, %rsp
; AVX2-NEXT: subq $128, %rsp ; AVX2-NEXT: subq $128, %rsp
; AVX2-NEXT: .Lcfi23: ; AVX2-NEXT: .Lcfi30:
; AVX2-NEXT: .cfi_offset %rbx, -56 ; AVX2-NEXT: .cfi_offset %rbx, -56
; AVX2-NEXT: .Lcfi24: ; AVX2-NEXT: .Lcfi31:
; AVX2-NEXT: .cfi_offset %r12, -48 ; AVX2-NEXT: .cfi_offset %r12, -48
; AVX2-NEXT: .Lcfi25: ; AVX2-NEXT: .Lcfi32:
; AVX2-NEXT: .cfi_offset %r13, -40 ; AVX2-NEXT: .cfi_offset %r13, -40
; AVX2-NEXT: .Lcfi26: ; AVX2-NEXT: .Lcfi33:
; AVX2-NEXT: .cfi_offset %r14, -32 ; AVX2-NEXT: .cfi_offset %r14, -32
; AVX2-NEXT: .Lcfi27: ; AVX2-NEXT: .Lcfi34:
; AVX2-NEXT: .cfi_offset %r15, -24 ; AVX2-NEXT: .cfi_offset %r15, -24
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
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; AVX2-NEXT: vpsraw $15, %ymm1, %ymm1 ; AVX2-NEXT: vpsraw $15, %ymm1, %ymm1
; AVX2-NEXT: leaq -40(%rbp), %rsp ; AVX2-NEXT: leaq -40(%rbp), %rsp
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12 ; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13 ; AVX2-NEXT: popq %r13
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15 ; AVX2-NEXT: popq %r15
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi35:
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i32_32i16: ; AVX512-LABEL: ext_i32_32i16:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: kmovd %edi, %k0 ; AVX512-NEXT: kmovd %edi, %k0
; AVX512-NEXT: vpmovm2w %k0, %zmm0 ; AVX512-NEXT: vpmovm2w %k0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i32 %a0 to <32 x i1> %1 = bitcast i32 %a0 to <32 x i1>
%2 = sext <32 x i1> %1 to <32 x i16> %2 = sext <32 x i1> %1 to <32 x i16>
ret <32 x i16> %2 ret <32 x i16> %2
} }
define <64 x i8> @ext_i64_64i8(i64 %a0) { define <64 x i8> @ext_i64_64i8(i64 %a0) {
; SSE2-SSSE3-LABEL: ext_i64_64i8: ; SSE2-SSSE3-LABEL: ext_i64_64i8:
; SSE2-SSSE3: # BB#0: ; SSE2-SSSE3: # BB#0:
; SSE2-SSSE3-NEXT: pushq %rbp ; SSE2-SSSE3-NEXT: pushq %rbp
; SSE2-SSSE3-NEXT: .Lcfi24: ; SSE2-SSSE3-NEXT: .Lcfi36:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 16 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 16
; SSE2-SSSE3-NEXT: pushq %r15 ; SSE2-SSSE3-NEXT: pushq %r15
; SSE2-SSSE3-NEXT: .Lcfi25: ; SSE2-SSSE3-NEXT: .Lcfi37:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 24 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 24
; SSE2-SSSE3-NEXT: pushq %r14 ; SSE2-SSSE3-NEXT: pushq %r14
; SSE2-SSSE3-NEXT: .Lcfi26: ; SSE2-SSSE3-NEXT: .Lcfi38:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 32 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 32
; SSE2-SSSE3-NEXT: pushq %r13 ; SSE2-SSSE3-NEXT: pushq %r13
; SSE2-SSSE3-NEXT: .Lcfi27: ; SSE2-SSSE3-NEXT: .Lcfi39:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 40 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 40
; SSE2-SSSE3-NEXT: pushq %r12 ; SSE2-SSSE3-NEXT: pushq %r12
; SSE2-SSSE3-NEXT: .Lcfi28: ; SSE2-SSSE3-NEXT: .Lcfi40:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 48 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 48
; SSE2-SSSE3-NEXT: pushq %rbx ; SSE2-SSSE3-NEXT: pushq %rbx
; SSE2-SSSE3-NEXT: .Lcfi29: ; SSE2-SSSE3-NEXT: .Lcfi41:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 56 ; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 56
; SSE2-SSSE3-NEXT: .Lcfi30: ; SSE2-SSSE3-NEXT: .Lcfi42:
; SSE2-SSSE3-NEXT: .cfi_offset %rbx, -56 ; SSE2-SSSE3-NEXT: .cfi_offset %rbx, -56
; SSE2-SSSE3-NEXT: .Lcfi31: ; SSE2-SSSE3-NEXT: .Lcfi43:
; SSE2-SSSE3-NEXT: .cfi_offset %r12, -48 ; SSE2-SSSE3-NEXT: .cfi_offset %r12, -48
; SSE2-SSSE3-NEXT: .Lcfi32: ; SSE2-SSSE3-NEXT: .Lcfi44:
; SSE2-SSSE3-NEXT: .cfi_offset %r13, -40 ; SSE2-SSSE3-NEXT: .cfi_offset %r13, -40
; SSE2-SSSE3-NEXT: .Lcfi33: ; SSE2-SSSE3-NEXT: .Lcfi45:
; SSE2-SSSE3-NEXT: .cfi_offset %r14, -32 ; SSE2-SSSE3-NEXT: .cfi_offset %r14, -32
; SSE2-SSSE3-NEXT: .Lcfi34: ; SSE2-SSSE3-NEXT: .Lcfi46:
; SSE2-SSSE3-NEXT: .cfi_offset %r15, -24 ; SSE2-SSSE3-NEXT: .cfi_offset %r15, -24
; SSE2-SSSE3-NEXT: .Lcfi35: ; SSE2-SSSE3-NEXT: .Lcfi47:
; SSE2-SSSE3-NEXT: .cfi_offset %rbp, -16 ; SSE2-SSSE3-NEXT: .cfi_offset %rbp, -16
; SSE2-SSSE3-NEXT: movw %di, -{{[0-9]+}}(%rsp) ; SSE2-SSSE3-NEXT: movw %di, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movq %rdi, %rax ; SSE2-SSSE3-NEXT: movq %rdi, %rax
; SSE2-SSSE3-NEXT: shrq $32, %rax ; SSE2-SSSE3-NEXT: shrq $32, %rax
; SSE2-SSSE3-NEXT: movw %ax, -{{[0-9]+}}(%rsp) ; SSE2-SSSE3-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movq %rdi, %rax ; SSE2-SSSE3-NEXT: movq %rdi, %rax
; SSE2-SSSE3-NEXT: shrq $48, %rax ; SSE2-SSSE3-NEXT: shrq $48, %rax
; SSE2-SSSE3-NEXT: movw %ax, -{{[0-9]+}}(%rsp) ; SSE2-SSSE3-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
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; SSE2-SSSE3-NEXT: movd %ebp, %xmm5 ; SSE2-SSSE3-NEXT: movd %ebp, %xmm5
; SSE2-SSSE3-NEXT: shrq $7, %rsi ; SSE2-SSSE3-NEXT: shrq $7, %rsi
; SSE2-SSSE3-NEXT: movd %esi, %xmm6 ; SSE2-SSSE3-NEXT: movd %esi, %xmm6
; SSE2-SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3],xmm5[4],xmm6[4],xmm5[5],xmm6[5],xmm5[6],xmm6[6],xmm5[7],xmm6[7] ; SSE2-SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3],xmm5[4],xmm6[4],xmm5[5],xmm6[5],xmm5[6],xmm6[6],xmm5[7],xmm6[7]
; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3] ; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1] ; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1]
; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0] ; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
; SSE2-SSSE3-NEXT: popq %rbx ; SSE2-SSSE3-NEXT: popq %rbx
; SSE2-SSSE3-NEXT: .Lcfi48:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 48
; SSE2-SSSE3-NEXT: popq %r12 ; SSE2-SSSE3-NEXT: popq %r12
; SSE2-SSSE3-NEXT: .Lcfi49:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 40
; SSE2-SSSE3-NEXT: popq %r13 ; SSE2-SSSE3-NEXT: popq %r13
; SSE2-SSSE3-NEXT: .Lcfi50:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 32
; SSE2-SSSE3-NEXT: popq %r14 ; SSE2-SSSE3-NEXT: popq %r14
; SSE2-SSSE3-NEXT: .Lcfi51:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 24
; SSE2-SSSE3-NEXT: popq %r15 ; SSE2-SSSE3-NEXT: popq %r15
; SSE2-SSSE3-NEXT: .Lcfi52:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 16
; SSE2-SSSE3-NEXT: popq %rbp ; SSE2-SSSE3-NEXT: popq %rbp
; SSE2-SSSE3-NEXT: .Lcfi53:
; SSE2-SSSE3-NEXT: .cfi_def_cfa_offset 8
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX1-LABEL: ext_i64_64i8: ; AVX1-LABEL: ext_i64_64i8:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi28: ; AVX1-NEXT: .Lcfi36:
; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi29: ; AVX1-NEXT: .Lcfi37:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: .Lcfi30: ; AVX1-NEXT: .Lcfi38:
; AVX1-NEXT: .cfi_def_cfa_register %rbp ; AVX1-NEXT: .cfi_def_cfa_register %rbp
; AVX1-NEXT: pushq %r15 ; AVX1-NEXT: pushq %r15
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %r13 ; AVX1-NEXT: pushq %r13
; AVX1-NEXT: pushq %r12 ; AVX1-NEXT: pushq %r12
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $128, %rsp ; AVX1-NEXT: subq $128, %rsp
; AVX1-NEXT: .Lcfi31: ; AVX1-NEXT: .Lcfi39:
; AVX1-NEXT: .cfi_offset %rbx, -56 ; AVX1-NEXT: .cfi_offset %rbx, -56
; AVX1-NEXT: .Lcfi32: ; AVX1-NEXT: .Lcfi40:
; AVX1-NEXT: .cfi_offset %r12, -48 ; AVX1-NEXT: .cfi_offset %r12, -48
; AVX1-NEXT: .Lcfi33: ; AVX1-NEXT: .Lcfi41:
; AVX1-NEXT: .cfi_offset %r13, -40 ; AVX1-NEXT: .cfi_offset %r13, -40
; AVX1-NEXT: .Lcfi34: ; AVX1-NEXT: .Lcfi42:
; AVX1-NEXT: .cfi_offset %r14, -32 ; AVX1-NEXT: .cfi_offset %r14, -32
; AVX1-NEXT: .Lcfi35: ; AVX1-NEXT: .Lcfi43:
; AVX1-NEXT: .cfi_offset %r15, -24 ; AVX1-NEXT: .cfi_offset %r15, -24
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX1-NEXT: shrq $32, %rdi ; AVX1-NEXT: shrq $32, %rdi
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX1-NEXT: movslq {{[0-9]+}}(%rsp), %rdx ; AVX1-NEXT: movslq {{[0-9]+}}(%rsp), %rdx
; AVX1-NEXT: movq %rdx, %rcx ; AVX1-NEXT: movq %rdx, %rcx
; AVX1-NEXT: shlq $47, %rcx ; AVX1-NEXT: shlq $47, %rcx
; AVX1-NEXT: sarq $63, %rcx ; AVX1-NEXT: sarq $63, %rcx
▲ Show 20 Lines • Show All 258 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: leaq -40(%rbp), %rsp ; AVX1-NEXT: leaq -40(%rbp), %rsp
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r12 ; AVX1-NEXT: popq %r12
; AVX1-NEXT: popq %r13 ; AVX1-NEXT: popq %r13
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: popq %r15 ; AVX1-NEXT: popq %r15
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi44:
; AVX1-NEXT: .cfi_def_cfa %rsp, 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: ext_i64_64i8: ; AVX2-LABEL: ext_i64_64i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi28: ; AVX2-NEXT: .Lcfi36:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi29: ; AVX2-NEXT: .Lcfi37:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: movq %rsp, %rbp
; AVX2-NEXT: .Lcfi30: ; AVX2-NEXT: .Lcfi38:
; AVX2-NEXT: .cfi_def_cfa_register %rbp ; AVX2-NEXT: .cfi_def_cfa_register %rbp
; AVX2-NEXT: pushq %r15 ; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %r13 ; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12 ; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: andq $-32, %rsp
; AVX2-NEXT: subq $128, %rsp ; AVX2-NEXT: subq $128, %rsp
; AVX2-NEXT: .Lcfi31: ; AVX2-NEXT: .Lcfi39:
; AVX2-NEXT: .cfi_offset %rbx, -56 ; AVX2-NEXT: .cfi_offset %rbx, -56
; AVX2-NEXT: .Lcfi32: ; AVX2-NEXT: .Lcfi40:
; AVX2-NEXT: .cfi_offset %r12, -48 ; AVX2-NEXT: .cfi_offset %r12, -48
; AVX2-NEXT: .Lcfi33: ; AVX2-NEXT: .Lcfi41:
; AVX2-NEXT: .cfi_offset %r13, -40 ; AVX2-NEXT: .cfi_offset %r13, -40
; AVX2-NEXT: .Lcfi34: ; AVX2-NEXT: .Lcfi42:
; AVX2-NEXT: .cfi_offset %r14, -32 ; AVX2-NEXT: .cfi_offset %r14, -32
; AVX2-NEXT: .Lcfi35: ; AVX2-NEXT: .Lcfi43:
; AVX2-NEXT: .cfi_offset %r15, -24 ; AVX2-NEXT: .cfi_offset %r15, -24
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX2-NEXT: shrq $32, %rdi ; AVX2-NEXT: shrq $32, %rdi
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp)
; AVX2-NEXT: movslq {{[0-9]+}}(%rsp), %rdx ; AVX2-NEXT: movslq {{[0-9]+}}(%rsp), %rdx
; AVX2-NEXT: movq %rdx, %rcx ; AVX2-NEXT: movq %rdx, %rcx
; AVX2-NEXT: shlq $47, %rcx ; AVX2-NEXT: shlq $47, %rcx
; AVX2-NEXT: sarq $63, %rcx ; AVX2-NEXT: sarq $63, %rcx
▲ Show 20 Lines • Show All 258 Lines • ▼ Show 20 Lines
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 ; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX2-NEXT: leaq -40(%rbp), %rsp ; AVX2-NEXT: leaq -40(%rbp), %rsp
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12 ; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13 ; AVX2-NEXT: popq %r13
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15 ; AVX2-NEXT: popq %r15
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi44:
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i64_64i8: ; AVX512-LABEL: ext_i64_64i8:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: kmovq %rdi, %k0 ; AVX512-NEXT: kmovq %rdi, %k0
; AVX512-NEXT: vpmovm2b %k0, %zmm0 ; AVX512-NEXT: vpmovm2b %k0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i64 %a0 to <64 x i1> %1 = bitcast i64 %a0 to <64 x i1>
%2 = sext <64 x i1> %1 to <64 x i8> %2 = sext <64 x i1> %1 to <64 x i8>
ret <64 x i8> %2 ret <64 x i8> %2
} }