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Differential D35844 Diff 109065 lib/CodeGen/MachineInstr.cpp

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lib/CodeGen/MachineInstr.cpp

Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines case MachineOperand::MO_RegisterLiveOut: {
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32; unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
// Deep compare of the two RegMasks // Deep compare of the two RegMasks
return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask); return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
} }
case MachineOperand::MO_MCSymbol: case MachineOperand::MO_MCSymbol:
return getMCSymbol() == Other.getMCSymbol(); return getMCSymbol() == Other.getMCSymbol();
case MachineOperand::MO_CFIIndex: case MachineOperand::MO_CFIIndex: {
return getCFIIndex() == Other.getCFIIndex(); const MachineFunction *MF = getParent()->getParent()->getParent();
const MachineFunction *OtherMF =
Other.getParent()->getParent()->getParent();
MCCFIInstruction Inst = MF->getFrameInstructions()[getCFIIndex()];
MCCFIInstruction OtherInst =
OtherMF->getFrameInstructions()[Other.getCFIIndex()];
MCCFIInstruction::OpType op = Inst.getOperation();
if (op != OtherInst.getOperation()) return false;
if (op == MCCFIInstruction::OpDefCfa || op == MCCFIInstruction::OpOffset ||
op == MCCFIInstruction::OpRestore ||
op == MCCFIInstruction::OpUndefined ||
op == MCCFIInstruction::OpSameValue ||
op == MCCFIInstruction::OpDefCfaRegister ||
op == MCCFIInstruction::OpRelOffset ||
op == MCCFIInstruction::OpRegister)
if (Inst.getRegister() != OtherInst.getRegister()) return false;
if (op == MCCFIInstruction::OpRegister)
if (Inst.getRegister2() != OtherInst.getRegister2()) return false;
if (op == MCCFIInstruction::OpDefCfa || op == MCCFIInstruction::OpOffset ||
op == MCCFIInstruction::OpRelOffset ||
op == MCCFIInstruction::OpDefCfaOffset ||
op == MCCFIInstruction::OpAdjustCfaOffset ||
op == MCCFIInstruction::OpGnuArgsSize)
if (Inst.getOffset() != OtherInst.getOffset()) return false;
MatzeBUnsubmitted
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This looks like a good candidate for a switch().

MatzeB: This looks like a good candidate for a `switch()`.
return true;
}
case MachineOperand::MO_Metadata: case MachineOperand::MO_Metadata:
return getMetadata() == Other.getMetadata(); return getMetadata() == Other.getMetadata();
case MachineOperand::MO_IntrinsicID: case MachineOperand::MO_IntrinsicID:
return getIntrinsicID() == Other.getIntrinsicID(); return getIntrinsicID() == Other.getIntrinsicID();
MatzeBUnsubmitted
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Keep case/default at the same indentation level as the switch.

MatzeB: Keep `case`/`default` at the same indentation level as the switch.
case MachineOperand::MO_Predicate: case MachineOperand::MO_Predicate:
return getPredicate() == Other.getPredicate(); return getPredicate() == Other.getPredicate();
MatzeBUnsubmitted
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As there are only 2 or 3 cases that are not handled yet, I would recommend to explicitely add cases for them and not add a default: at all. The benefit of this is that when someone adds new OpTypes in the future he will immediately get a compiler warning for a missing case when he forgets to add a case here.

MatzeB: As there are only 2 or 3 cases that are not handled yet, I would recommend to explicitely add…
} }
llvm_unreachable("Invalid machine operand type"); llvm_unreachable("Invalid machine operand type");
} }
// Note: this must stay exactly in sync with isIdenticalTo above. // Note: this must stay exactly in sync with isIdenticalTo above.
hash_code llvm::hash_value(const MachineOperand &MO) { hash_code llvm::hash_value(const MachineOperand &MO) {
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
Show All 26 Lines return hash_combine(MO.getType(), MO.getTargetFlags(),
MO.getBlockAddress(), MO.getOffset()); MO.getBlockAddress(), MO.getOffset());
case MachineOperand::MO_RegisterMask: case MachineOperand::MO_RegisterMask:
case MachineOperand::MO_RegisterLiveOut: case MachineOperand::MO_RegisterLiveOut:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
case MachineOperand::MO_Metadata: case MachineOperand::MO_Metadata:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
case MachineOperand::MO_MCSymbol: case MachineOperand::MO_MCSymbol:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
case MachineOperand::MO_CFIIndex: case MachineOperand::MO_CFIIndex: {
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex()); const MachineFunction *MF = MO.getParent()->getParent()->getParent();
MCCFIInstruction Inst = MF->getFrameInstructions()[MO.getCFIIndex()];
return hash_combine(MO.getType(), MO.getTargetFlags(), Inst.getOperation(),
Inst.getRegister(), Inst.getRegister2(),
Inst.getOffset());
}
case MachineOperand::MO_IntrinsicID: case MachineOperand::MO_IntrinsicID:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID()); return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
case MachineOperand::MO_Predicate: case MachineOperand::MO_Predicate:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate()); return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
} }
llvm_unreachable("Invalid machine operand type"); llvm_unreachable("Invalid machine operand type");
} }
▲ Show 20 Lines • Show All 2,026 Lines • Show Last 20 Lines