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Differential D35844 Diff 108098 test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll

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test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll

Show First 20 Lines • Show All 497 Lines • ▼ Show 20 Lines
; AVX512-NEXT: vpinsrb $10, %ebp, %xmm0, %xmm0 ; AVX512-NEXT: vpinsrb $10, %ebp, %xmm0, %xmm0
; AVX512-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 ; AVX512-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0
; AVX512-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0 ; AVX512-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
; AVX512-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0 ; AVX512-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0
; AVX512-NEXT: vpinsrb $14, %edx, %xmm0, %xmm0 ; AVX512-NEXT: vpinsrb $14, %edx, %xmm0, %xmm0
; AVX512-NEXT: vpinsrb $15, %r9d, %xmm0, %xmm0 ; AVX512-NEXT: vpinsrb $15, %r9d, %xmm0, %xmm0
; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: popq %rbx ; AVX512-NEXT: popq %rbx
; AVX512-NEXT: .Lcfi12:
; AVX512-NEXT: .cfi_def_cfa_offset 48
; AVX512-NEXT: popq %r12 ; AVX512-NEXT: popq %r12
; AVX512-NEXT: .Lcfi13:
; AVX512-NEXT: .cfi_def_cfa_offset 40
; AVX512-NEXT: popq %r13 ; AVX512-NEXT: popq %r13
; AVX512-NEXT: .Lcfi14:
; AVX512-NEXT: .cfi_def_cfa_offset 32
; AVX512-NEXT: popq %r14 ; AVX512-NEXT: popq %r14
; AVX512-NEXT: .Lcfi15:
; AVX512-NEXT: .cfi_def_cfa_offset 24
; AVX512-NEXT: popq %r15 ; AVX512-NEXT: popq %r15
; AVX512-NEXT: .Lcfi16:
; AVX512-NEXT: .cfi_def_cfa_offset 16
; AVX512-NEXT: popq %rbp ; AVX512-NEXT: popq %rbp
; AVX512-NEXT: .Lcfi17:
; AVX512-NEXT: .cfi_def_cfa_offset 8
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i16 %a0 to <16 x i1> %1 = bitcast i16 %a0 to <16 x i1>
%2 = zext <16 x i1> %1 to <16 x i8> %2 = zext <16 x i1> %1 to <16 x i8>
ret <16 x i8> %2 ret <16 x i8> %2
} }
; ;
; 256-bit vectors ; 256-bit vectors
▲ Show 20 Lines • Show All 743 Lines • ▼ Show 20 Lines
; AVX1-NEXT: andl $1, %eax ; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1
; AVX1-NEXT: shrl $15, %edi ; AVX1-NEXT: shrl $15, %edi
; AVX1-NEXT: andl $1, %edi ; AVX1-NEXT: andl $1, %edi
; AVX1-NEXT: vpinsrb $15, %edi, %xmm1, %xmm1 ; AVX1-NEXT: vpinsrb $15, %edi, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: movq %rbp, %rsp ; AVX1-NEXT: movq %rbp, %rsp
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi3:
; AVX1-NEXT: .cfi_def_cfa %rsp, 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: ext_i32_32i8: ; AVX2-LABEL: ext_i32_32i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi0: ; AVX2-NEXT: .Lcfi0:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi1: ; AVX2-NEXT: .Lcfi1:
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
; AVX2-NEXT: andl $1, %eax ; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrb $14, %eax, %xmm1, %xmm1
; AVX2-NEXT: shrl $15, %edi ; AVX2-NEXT: shrl $15, %edi
; AVX2-NEXT: andl $1, %edi ; AVX2-NEXT: andl $1, %edi
; AVX2-NEXT: vpinsrb $15, %edi, %xmm1, %xmm1 ; AVX2-NEXT: vpinsrb $15, %edi, %xmm1, %xmm1
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: movq %rbp, %rsp ; AVX2-NEXT: movq %rbp, %rsp
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi3:
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i32_32i8: ; AVX512-LABEL: ext_i32_32i8:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: kmovd %edi, %k1 ; AVX512-NEXT: kmovd %edi, %k1
; AVX512-NEXT: vmovdqu8 {{.*}}(%rip), %ymm0 {%k1} {z} ; AVX512-NEXT: vmovdqu8 {{.*}}(%rip), %ymm0 {%k1} {z}
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i32 %a0 to <32 x i1> %1 = bitcast i32 %a0 to <32 x i1>
▲ Show 20 Lines • Show All 598 Lines • ▼ Show 20 Lines
; SSE2-SSSE3-NEXT: pand %xmm4, %xmm2 ; SSE2-SSSE3-NEXT: pand %xmm4, %xmm2
; SSE2-SSSE3-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15] ; SSE2-SSSE3-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15]
; SSE2-SSSE3-NEXT: pand %xmm4, %xmm3 ; SSE2-SSSE3-NEXT: pand %xmm4, %xmm3
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX1-LABEL: ext_i32_32i16: ; AVX1-LABEL: ext_i32_32i16:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi3:
; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi4: ; AVX1-NEXT: .Lcfi4:
; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi5:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: .Lcfi5: ; AVX1-NEXT: .Lcfi6:
; AVX1-NEXT: .cfi_def_cfa_register %rbp ; AVX1-NEXT: .cfi_def_cfa_register %rbp
; AVX1-NEXT: pushq %r15 ; AVX1-NEXT: pushq %r15
; AVX1-NEXT: pushq %r14 ; AVX1-NEXT: pushq %r14
; AVX1-NEXT: pushq %r13 ; AVX1-NEXT: pushq %r13
; AVX1-NEXT: pushq %r12 ; AVX1-NEXT: pushq %r12
; AVX1-NEXT: pushq %rbx ; AVX1-NEXT: pushq %rbx
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $128, %rsp ; AVX1-NEXT: subq $128, %rsp
; AVX1-NEXT: .Lcfi6:
; AVX1-NEXT: .cfi_offset %rbx, -56
; AVX1-NEXT: .Lcfi7: ; AVX1-NEXT: .Lcfi7:
; AVX1-NEXT: .cfi_offset %r12, -48 ; AVX1-NEXT: .cfi_offset %rbx, -56
; AVX1-NEXT: .Lcfi8: ; AVX1-NEXT: .Lcfi8:
; AVX1-NEXT: .cfi_offset %r13, -40 ; AVX1-NEXT: .cfi_offset %r12, -48
; AVX1-NEXT: .Lcfi9: ; AVX1-NEXT: .Lcfi9:
; AVX1-NEXT: .cfi_offset %r14, -32 ; AVX1-NEXT: .cfi_offset %r13, -40
; AVX1-NEXT: .Lcfi10: ; AVX1-NEXT: .Lcfi10:
; AVX1-NEXT: .cfi_offset %r14, -32
; AVX1-NEXT: .Lcfi11:
; AVX1-NEXT: .cfi_offset %r15, -24 ; AVX1-NEXT: .cfi_offset %r15, -24
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX1-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1 ; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1
; AVX1-NEXT: leaq -40(%rbp), %rsp ; AVX1-NEXT: leaq -40(%rbp), %rsp
; AVX1-NEXT: popq %rbx ; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r12 ; AVX1-NEXT: popq %r12
; AVX1-NEXT: popq %r13 ; AVX1-NEXT: popq %r13
; AVX1-NEXT: popq %r14 ; AVX1-NEXT: popq %r14
; AVX1-NEXT: popq %r15 ; AVX1-NEXT: popq %r15
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi12:
; AVX1-NEXT: .cfi_def_cfa %rsp, 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: ext_i32_32i16: ; AVX2-LABEL: ext_i32_32i16:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi3:
; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi4: ; AVX2-NEXT: .Lcfi4:
; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi5:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: movq %rsp, %rbp
; AVX2-NEXT: .Lcfi5: ; AVX2-NEXT: .Lcfi6:
; AVX2-NEXT: .cfi_def_cfa_register %rbp ; AVX2-NEXT: .cfi_def_cfa_register %rbp
; AVX2-NEXT: pushq %r15 ; AVX2-NEXT: pushq %r15
; AVX2-NEXT: pushq %r14 ; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %r13 ; AVX2-NEXT: pushq %r13
; AVX2-NEXT: pushq %r12 ; AVX2-NEXT: pushq %r12
; AVX2-NEXT: pushq %rbx ; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: andq $-32, %rsp
; AVX2-NEXT: subq $128, %rsp ; AVX2-NEXT: subq $128, %rsp
; AVX2-NEXT: .Lcfi6:
; AVX2-NEXT: .cfi_offset %rbx, -56
; AVX2-NEXT: .Lcfi7: ; AVX2-NEXT: .Lcfi7:
; AVX2-NEXT: .cfi_offset %r12, -48 ; AVX2-NEXT: .cfi_offset %rbx, -56
; AVX2-NEXT: .Lcfi8: ; AVX2-NEXT: .Lcfi8:
; AVX2-NEXT: .cfi_offset %r13, -40 ; AVX2-NEXT: .cfi_offset %r12, -48
; AVX2-NEXT: .Lcfi9: ; AVX2-NEXT: .Lcfi9:
; AVX2-NEXT: .cfi_offset %r14, -32 ; AVX2-NEXT: .cfi_offset %r13, -40
; AVX2-NEXT: .Lcfi10: ; AVX2-NEXT: .Lcfi10:
; AVX2-NEXT: .cfi_offset %r14, -32
; AVX2-NEXT: .Lcfi11:
; AVX2-NEXT: .cfi_offset %r15, -24 ; AVX2-NEXT: .cfi_offset %r15, -24
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill ; AVX2-NEXT: movl %edi, {{[0-9]+}}(%rsp) # 4-byte Spill
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX2-NEXT: leaq -40(%rbp), %rsp ; AVX2-NEXT: leaq -40(%rbp), %rsp
; AVX2-NEXT: popq %rbx ; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r12 ; AVX2-NEXT: popq %r12
; AVX2-NEXT: popq %r13 ; AVX2-NEXT: popq %r13
; AVX2-NEXT: popq %r14 ; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %r15 ; AVX2-NEXT: popq %r15
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi12:
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i32_32i16: ; AVX512-LABEL: ext_i32_32i16:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: kmovd %edi, %k1 ; AVX512-NEXT: kmovd %edi, %k1
; AVX512-NEXT: vmovdqu16 {{.*}}(%rip), %zmm0 {%k1} {z} ; AVX512-NEXT: vmovdqu16 {{.*}}(%rip), %zmm0 {%k1} {z}
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i32 %a0 to <32 x i1> %1 = bitcast i32 %a0 to <32 x i1>
▲ Show 20 Lines • Show All 325 Lines • ▼ Show 20 Lines
; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3] ; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3]
; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1] ; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]
; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0] ; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX1-LABEL: ext_i64_64i8: ; AVX1-LABEL: ext_i64_64i8:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: .Lcfi11: ; AVX1-NEXT: .Lcfi13:
; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: .Lcfi12: ; AVX1-NEXT: .Lcfi14:
; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: .Lcfi13: ; AVX1-NEXT: .Lcfi15:
; AVX1-NEXT: .cfi_def_cfa_register %rbp ; AVX1-NEXT: .cfi_def_cfa_register %rbp
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $64, %rsp ; AVX1-NEXT: subq $64, %rsp
; AVX1-NEXT: movl %edi, %eax ; AVX1-NEXT: movl %edi, %eax
; AVX1-NEXT: shrl $17, %eax ; AVX1-NEXT: shrl $17, %eax
; AVX1-NEXT: andl $1, %eax ; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: movl %edi, %ecx ; AVX1-NEXT: movl %edi, %ecx
; AVX1-NEXT: shrl $16, %ecx ; AVX1-NEXT: shrl $16, %ecx
▲ Show 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
; AVX1-NEXT: andl $1, %eax ; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2 ; AVX1-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2
; AVX1-NEXT: shrq $47, %rdi ; AVX1-NEXT: shrq $47, %rdi
; AVX1-NEXT: andl $1, %edi ; AVX1-NEXT: andl $1, %edi
; AVX1-NEXT: vpinsrb $15, %edi, %xmm2, %xmm2 ; AVX1-NEXT: vpinsrb $15, %edi, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: movq %rbp, %rsp ; AVX1-NEXT: movq %rbp, %rsp
; AVX1-NEXT: popq %rbp ; AVX1-NEXT: popq %rbp
; AVX1-NEXT: .Lcfi16:
; AVX1-NEXT: .cfi_def_cfa %rsp, 8
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: ext_i64_64i8: ; AVX2-LABEL: ext_i64_64i8:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: pushq %rbp ; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: .Lcfi11: ; AVX2-NEXT: .Lcfi13:
; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: .Lcfi12: ; AVX2-NEXT: .Lcfi14:
; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: movq %rsp, %rbp
; AVX2-NEXT: .Lcfi13: ; AVX2-NEXT: .Lcfi15:
; AVX2-NEXT: .cfi_def_cfa_register %rbp ; AVX2-NEXT: .cfi_def_cfa_register %rbp
; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: andq $-32, %rsp
; AVX2-NEXT: subq $64, %rsp ; AVX2-NEXT: subq $64, %rsp
; AVX2-NEXT: movl %edi, %eax ; AVX2-NEXT: movl %edi, %eax
; AVX2-NEXT: shrl $17, %eax ; AVX2-NEXT: shrl $17, %eax
; AVX2-NEXT: andl $1, %eax ; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: movl %edi, %ecx ; AVX2-NEXT: movl %edi, %ecx
; AVX2-NEXT: shrl $16, %ecx ; AVX2-NEXT: shrl $16, %ecx
▲ Show 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
; AVX2-NEXT: andl $1, %eax ; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2 ; AVX2-NEXT: vpinsrb $14, %eax, %xmm2, %xmm2
; AVX2-NEXT: shrq $47, %rdi ; AVX2-NEXT: shrq $47, %rdi
; AVX2-NEXT: andl $1, %edi ; AVX2-NEXT: andl $1, %edi
; AVX2-NEXT: vpinsrb $15, %edi, %xmm2, %xmm2 ; AVX2-NEXT: vpinsrb $15, %edi, %xmm2, %xmm2
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX2-NEXT: movq %rbp, %rsp ; AVX2-NEXT: movq %rbp, %rsp
; AVX2-NEXT: popq %rbp ; AVX2-NEXT: popq %rbp
; AVX2-NEXT: .Lcfi16:
; AVX2-NEXT: .cfi_def_cfa %rsp, 8
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: ext_i64_64i8: ; AVX512-LABEL: ext_i64_64i8:
; AVX512: # BB#0: ; AVX512: # BB#0:
; AVX512-NEXT: kmovq %rdi, %k1 ; AVX512-NEXT: kmovq %rdi, %k1
; AVX512-NEXT: vmovdqu8 {{.*}}(%rip), %zmm0 {%k1} {z} ; AVX512-NEXT: vmovdqu8 {{.*}}(%rip), %zmm0 {%k1} {z}
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = bitcast i64 %a0 to <64 x i1> %1 = bitcast i64 %a0 to <64 x i1>
%2 = zext <64 x i1> %1 to <64 x i8> %2 = zext <64 x i1> %1 to <64 x i8>
ret <64 x i8> %2 ret <64 x i8> %2
} }