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llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
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| let isCommutable = 1 in { | let isCommutable = 1 in { | ||||
| def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; | def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; | ||||
| def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; | def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; | ||||
| } // End isCommutable = 1 | } // End isCommutable = 1 | ||||
| } // End SubtargetPredicate = isCIVI | } // End SubtargetPredicate = isCIVI | ||||
| let SubtargetPredicate = isVI in { | let SubtargetPredicate = Has16BitInsts in { | ||||
| let isCommutable = 1 in { | let isCommutable = 1 in { | ||||
| def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; | def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; | ||||
| def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>; | def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>; | ||||
| def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>; | def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>; | ||||
| def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>; | def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>; | ||||
| def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>; | def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>; | ||||
| def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; | def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; | ||||
| def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>; | def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>; | ||||
| def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>; | def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>; | ||||
| } // End isCommutable = 1 | } // End isCommutable = 1 | ||||
| } // End SubtargetPredicate = Has16BitInsts | |||||
| let SubtargetPredicate = isVI in { | |||||
| def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | ||||
| } // End SubtargetPredicate = isVI | } // End SubtargetPredicate = isVI | ||||
| let Predicates = [isVI] in { | let Predicates = [Has16BitInsts] in { | ||||
| multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, | multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, | ||||
| Instruction inst, SDPatternOperator op3> { | Instruction inst, SDPatternOperator op3> { | ||||
| def : Pat< | def : Pat< | ||||
| (op2 (op1 i16:$src0, i16:$src1), i16:$src2), | (op2 (op1 i16:$src0, i16:$src1), i16:$src2), | ||||
| (inst i16:$src0, i16:$src1, i16:$src2) | (inst i16:$src0, i16:$src1, i16:$src2) | ||||
| >; | >; | ||||
| def : Pat< | def : Pat< | ||||
| (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), | (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), | ||||
| (inst i16:$src0, i16:$src1, i16:$src2) | (inst i16:$src0, i16:$src1, i16:$src2) | ||||
| >; | >; | ||||
| def : Pat< | def : Pat< | ||||
| (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), | (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), | ||||
| (REG_SEQUENCE VReg_64, | (REG_SEQUENCE VReg_64, | ||||
| (inst i16:$src0, i16:$src1, i16:$src2), sub0, | (inst i16:$src0, i16:$src1, i16:$src2), sub0, | ||||
| (V_MOV_B32_e32 (i32 0)), sub1) | (V_MOV_B32_e32 (i32 0)), sub1) | ||||
| >; | >; | ||||
| } | } | ||||
| defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>; | defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>; | ||||
| defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>; | defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>; | ||||
| } // End Predicates = [isVI] | } // End Predicates = [Has16BitInsts] | ||||
| let SubtargetPredicate = isGFX9 in { | let SubtargetPredicate = isGFX9 in { | ||||
| def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16>>; | def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16>>; | ||||
| def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | ||||
| def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | ||||
| def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | ||||
| def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | ||||
| def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; | ||||
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