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lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
| Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines | inline bool isKernel(CallingConv::ID CC) { | ||||
| default: | default: | ||||
| return false; | return false; | ||||
| } | } | ||||
| } | } | ||||
| bool isSI(const MCSubtargetInfo &STI); | bool isSI(const MCSubtargetInfo &STI); | ||||
| bool isCI(const MCSubtargetInfo &STI); | bool isCI(const MCSubtargetInfo &STI); | ||||
| bool isVI(const MCSubtargetInfo &STI); | bool isVI(const MCSubtargetInfo &STI); | ||||
| bool isGFX9(const MCSubtargetInfo &STI); | |||||
| /// \brief Is Reg - scalar register | |||||
| bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI); | |||||
| /// If \p Reg is a pseudo reg, return the correct hardware register given | /// If \p Reg is a pseudo reg, return the correct hardware register given | ||||
| /// \p STI otherwise return \p Reg. | /// \p STI otherwise return \p Reg. | ||||
| unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); | unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); | ||||
| /// \brief Convert hardware register \p Reg to a pseudo register | /// \brief Convert hardware register \p Reg to a pseudo register | ||||
| LLVM_READNONE | LLVM_READNONE | ||||
| unsigned mc2PseudoReg(unsigned Reg); | unsigned mc2PseudoReg(unsigned Reg); | ||||
| ▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines | |||||