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lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
| Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines | uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, | ||||
| SmallVectorImpl<MCFixup> &Fixups, | SmallVectorImpl<MCFixup> &Fixups, | ||||
| const MCSubtargetInfo &STI) const override; | const MCSubtargetInfo &STI) const override; | ||||
| /// \brief Use a fixup to encode the simm16 field for SOPP branch | /// \brief Use a fixup to encode the simm16 field for SOPP branch | ||||
| /// instructions. | /// instructions. | ||||
| unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, | unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, | ||||
| SmallVectorImpl<MCFixup> &Fixups, | SmallVectorImpl<MCFixup> &Fixups, | ||||
| const MCSubtargetInfo &STI) const override; | const MCSubtargetInfo &STI) const override; | ||||
| unsigned getSDWA9SrcEncoding(const MCInst &MI, unsigned OpNo, | |||||
| SmallVectorImpl<MCFixup> &Fixups, | |||||
| const MCSubtargetInfo &STI) const override; | |||||
| unsigned getSDWA9VopcDstEncoding(const MCInst &MI, unsigned OpNo, | |||||
| SmallVectorImpl<MCFixup> &Fixups, | |||||
| const MCSubtargetInfo &STI) const override; | |||||
| }; | }; | ||||
| } // end anonymous namespace | } // end anonymous namespace | ||||
| MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, | MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, | ||||
| const MCRegisterInfo &MRI, | const MCRegisterInfo &MRI, | ||||
| MCContext &Ctx) { | MCContext &Ctx) { | ||||
| return new SIMCCodeEmitter(MCII, MRI, Ctx); | return new SIMCCodeEmitter(MCII, MRI, Ctx); | ||||
| ▲ Show 20 Lines • Show All 234 Lines • ▼ Show 20 Lines | if (MO.isExpr()) { | ||||
| MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br; | MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br; | ||||
| Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); | Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); | ||||
| return 0; | return 0; | ||||
| } | } | ||||
| return getMachineOpValue(MI, MO, Fixups, STI); | return getMachineOpValue(MI, MO, Fixups, STI); | ||||
| } | } | ||||
| unsigned | |||||
| SIMCCodeEmitter::getSDWA9SrcEncoding(const MCInst &MI, unsigned OpNo, | |||||
| SmallVectorImpl<MCFixup> &Fixups, | |||||
| const MCSubtargetInfo &STI) const { | |||||
| uint64_t RegEnc = 0; | |||||
| const MCOperand &MO = MI.getOperand(OpNo); | |||||
| unsigned Reg = MO.getReg(); | |||||
| RegEnc |= MRI.getEncodingValue(Reg); | |||||
| RegEnc &= SDWA9_SRC_REG_MASK; | |||||
| if (AMDGPU::isSGPR(Reg, &MRI)) { | |||||
| RegEnc |= SDWA9_SRC_SGPR_MASK; | |||||
| } | |||||
| return RegEnc; | |||||
| } | |||||
| unsigned | |||||
| SIMCCodeEmitter::getSDWA9VopcDstEncoding(const MCInst &MI, unsigned OpNo, | |||||
| SmallVectorImpl<MCFixup> &Fixups, | |||||
| const MCSubtargetInfo &STI) const { | |||||
| uint64_t RegEnc = 0; | |||||
| const MCOperand &MO = MI.getOperand(OpNo); | |||||
| unsigned Reg = MO.getReg(); | |||||
| if (Reg != AMDGPU::VCC) { | |||||
| RegEnc |= MRI.getEncodingValue(Reg); | |||||
| RegEnc &= SDWA9_VOPC_DST_REG_MASK; | |||||
| RegEnc |= SDWA9_VOPC_DST_VCC_MASK; | |||||
| } | |||||
| return RegEnc; | |||||
| } | |||||
| uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, | uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, | ||||
| const MCOperand &MO, | const MCOperand &MO, | ||||
| SmallVectorImpl<MCFixup> &Fixups, | SmallVectorImpl<MCFixup> &Fixups, | ||||
| const MCSubtargetInfo &STI) const { | const MCSubtargetInfo &STI) const { | ||||
| if (MO.isReg()) | if (MO.isReg()) | ||||
| return MRI.getEncodingValue(MO.getReg()); | return MRI.getEncodingValue(MO.getReg()); | ||||
| if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) { | if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) { | ||||
| Show All 28 Lines | |||||