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lib/Target/Mips/AsmParser/MipsAsmParser.cpp
| Show First 20 Lines • Show All 2,129 Lines • ▼ Show 20 Lines | MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, | ||||
| case Mips::LWM_MM: | case Mips::LWM_MM: | ||||
| return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail | return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail | ||||
| : MER_Success; | : MER_Success; | ||||
| case Mips::JalOneReg: | case Mips::JalOneReg: | ||||
| case Mips::JalTwoReg: | case Mips::JalTwoReg: | ||||
| return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; | return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; | ||||
| case Mips::BneImm: | case Mips::BneImm: | ||||
| case Mips::BeqImm: | case Mips::BeqImm: | ||||
| case Mips::BEQLImmMacro: | |||||
| case Mips::BNELImmMacro: | |||||
| return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; | return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; | ||||
| case Mips::BLT: | case Mips::BLT: | ||||
| case Mips::BLE: | case Mips::BLE: | ||||
| case Mips::BGE: | case Mips::BGE: | ||||
| case Mips::BGT: | case Mips::BGT: | ||||
| case Mips::BLTU: | case Mips::BLTU: | ||||
| case Mips::BLEU: | case Mips::BLEU: | ||||
| case Mips::BGEU: | case Mips::BGEU: | ||||
| ▲ Show 20 Lines • Show All 618 Lines • ▼ Show 20 Lines | bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, | ||||
| const MCOperand &ImmOp = Inst.getOperand(1); | const MCOperand &ImmOp = Inst.getOperand(1); | ||||
| assert(ImmOp.isImm() && "expected immediate operand kind"); | assert(ImmOp.isImm() && "expected immediate operand kind"); | ||||
| const MCOperand &MemOffsetOp = Inst.getOperand(2); | const MCOperand &MemOffsetOp = Inst.getOperand(2); | ||||
| assert((MemOffsetOp.isImm() || MemOffsetOp.isExpr()) && | assert((MemOffsetOp.isImm() || MemOffsetOp.isExpr()) && | ||||
| "expected immediate or expression operand"); | "expected immediate or expression operand"); | ||||
| bool IsLikely = false; | |||||
| unsigned OpCode = 0; | unsigned OpCode = 0; | ||||
| switch(Inst.getOpcode()) { | switch(Inst.getOpcode()) { | ||||
| case Mips::BneImm: | case Mips::BneImm: | ||||
| OpCode = Mips::BNE; | OpCode = Mips::BNE; | ||||
| break; | break; | ||||
| case Mips::BeqImm: | case Mips::BeqImm: | ||||
| OpCode = Mips::BEQ; | OpCode = Mips::BEQ; | ||||
| break; | break; | ||||
| case Mips::BEQLImmMacro: | |||||
| OpCode = Mips::BEQL; | |||||
| IsLikely = true; | |||||
| break; | |||||
| case Mips::BNELImmMacro: | |||||
| OpCode = Mips::BNEL; | |||||
| IsLikely = true; | |||||
| break; | |||||
| default: | default: | ||||
| llvm_unreachable("Unknown immediate branch pseudo-instruction."); | llvm_unreachable("Unknown immediate branch pseudo-instruction."); | ||||
| break; | break; | ||||
| } | } | ||||
| int64_t ImmValue = ImmOp.getImm(); | int64_t ImmValue = ImmOp.getImm(); | ||||
| if (ImmValue == 0) | if (ImmValue == 0) { | ||||
| if (IsLikely) { | |||||
| TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, | |||||
| MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); | |||||
| TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); | |||||
| } else | |||||
| TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, | TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, | ||||
| STI); | STI); | ||||
| else { | } else { | ||||
| warnIfNoMacro(IDLoc); | warnIfNoMacro(IDLoc); | ||||
| unsigned ATReg = getATReg(IDLoc); | unsigned ATReg = getATReg(IDLoc); | ||||
| if (!ATReg) | if (!ATReg) | ||||
| return true; | return true; | ||||
| if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, | if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, | ||||
| IDLoc, Out, STI)) | IDLoc, Out, STI)) | ||||
| return true; | return true; | ||||
| if (IsLikely) { | |||||
| TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, | |||||
vkalintiris: This line is too big, can you split it? | |||||
| MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); | |||||
| TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); | |||||
| } else | |||||
| TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI); | TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI); | ||||
| } | } | ||||
| return false; | return false; | ||||
| } | } | ||||
| void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, | void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, | ||||
| const MCSubtargetInfo *STI, bool IsLoad, | const MCSubtargetInfo *STI, bool IsLoad, | ||||
| bool IsImmOpnd) { | bool IsImmOpnd) { | ||||
| if (IsLoad) { | if (IsLoad) { | ||||
| ▲ Show 20 Lines • Show All 3,967 Lines • Show Last 20 Lines | |||||
This line is too big, can you split it?