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lib/Target/Mips/MipsSubtarget.cpp
| Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines | MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, | ||||
| PreviousInMips16Mode = InMips16Mode; | PreviousInMips16Mode = InMips16Mode; | ||||
| // Initialize scheduling itinerary for the specified CPU. | // Initialize scheduling itinerary for the specified CPU. | ||||
| InstrItins = getInstrItineraryForCPU(CPUName); | InstrItins = getInstrItineraryForCPU(CPUName); | ||||
| // Set MipsABI if it hasn't been set yet. | // Set MipsABI if it hasn't been set yet. | ||||
| if (MipsABI == UnknownABI) | if (MipsABI == UnknownABI) | ||||
| MipsABI = hasMips64() ? N64 : O32; | MipsABI = isGP64bit() ? N64 : O32; | ||||
| // Check if Architecture and ABI are compatible. | // Check if Architecture and ABI are compatible. | ||||
| assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) || | assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || | ||||
| (hasMips64() && (isABI_N32() || isABI_N64()))) && | (isGP64bit() && (isABI_N32() || isABI_N64()))) && | ||||
| "Invalid Arch & ABI pair."); | "Invalid Arch & ABI pair."); | ||||
| if (hasMSA() && !isFP64bit()) | if (hasMSA() && !isFP64bit()) | ||||
| report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). " | report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). " | ||||
| "See -mattr=+fp64.", | "See -mattr=+fp64.", | ||||
| false); | false); | ||||
| // Is the target system Linux ? | // Is the target system Linux ? | ||||
| if (TT.find("linux") == std::string::npos) | if (TT.find("linux") == std::string::npos) | ||||
| IsLinux = false; | IsLinux = false; | ||||
| // Set UseSmallSection. | // Set UseSmallSection. | ||||
| UseSmallSection = !IsLinux && (RM == Reloc::Static); | UseSmallSection = !IsLinux && (RM == Reloc::Static); | ||||
| // set some subtarget specific features | // set some subtarget specific features | ||||
| if (inMips16Mode()) | if (inMips16Mode()) | ||||
| HasBitCount=false; | HasBitCount=false; | ||||
| } | } | ||||
| bool | bool | ||||
| MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, | MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, | ||||
| TargetSubtargetInfo::AntiDepBreakMode &Mode, | TargetSubtargetInfo::AntiDepBreakMode &Mode, | ||||
| RegClassVector &CriticalPathRCs) const { | RegClassVector &CriticalPathRCs) const { | ||||
| Mode = TargetSubtargetInfo::ANTIDEP_NONE; | Mode = TargetSubtargetInfo::ANTIDEP_NONE; | ||||
| CriticalPathRCs.clear(); | CriticalPathRCs.clear(); | ||||
| CriticalPathRCs.push_back(hasMips64() ? | CriticalPathRCs.push_back(isGP64bit() ? | ||||
| &Mips::GPR64RegClass : &Mips::GPR32RegClass); | &Mips::GPR64RegClass : &Mips::GPR32RegClass); | ||||
| return OptLevel >= CodeGenOpt::Aggressive; | return OptLevel >= CodeGenOpt::Aggressive; | ||||
| } | } | ||||
| //FIXME: This logic for reseting the subtarget along with | //FIXME: This logic for reseting the subtarget along with | ||||
| // the helper classes can probably be simplified but there are a lot of | // the helper classes can probably be simplified but there are a lot of | ||||
| // cases so we will defer rewriting this to later. | // cases so we will defer rewriting this to later. | ||||
| // | // | ||||
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