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lib/Target/Mips/Mips64InstrInfo.td
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| def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>; | def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>; | ||||
| def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>; | def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>; | ||||
| /// Sign Ext In Register Instructions. | /// Sign Ext In Register Instructions. | ||||
| def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>; | def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>; | ||||
| def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>; | def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>; | ||||
| } | } | ||||
| let Predicates = [HasMips64] in { | |||||
| /// Count Leading | /// Count Leading | ||||
| def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>; | def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>; | ||||
| def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>; | def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>; | ||||
| /// Double Word Swap Bytes/HalfWords | /// Double Word Swap Bytes/HalfWords | ||||
| def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>; | def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>; | ||||
| def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>; | def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>; | ||||
| } | |||||
| def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; | def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; | ||||
| let isCodeGenOnly = 1 in | let isCodeGenOnly = 1 in | ||||
| def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; | def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; | ||||
| def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>; | def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>; | ||||
| def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>; | def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>; | ||||
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