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lib/Target/ARM/ARMInstrInfo.td
| Show First 20 Lines • Show All 324 Lines • ▼ Show 20 Lines | |||||
| def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" | def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" | ||||
| "!Subtarget->useNEONForSinglePrecisionFP()">; | "!Subtarget->useNEONForSinglePrecisionFP()">; | ||||
| def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" | def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" | ||||
| "Subtarget->useNEONForSinglePrecisionFP()">; | "Subtarget->useNEONForSinglePrecisionFP()">; | ||||
| def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; | def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; | ||||
| def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; | def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; | ||||
| def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; | |||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // ARM Flag Definitions. | // ARM Flag Definitions. | ||||
| class RegConstraint<string C> { | class RegConstraint<string C> { | ||||
| string Constraints = C; | string Constraints = C; | ||||
| } | } | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
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